5PB1104CMG18 Renesas

1.8V to 3.3V High-Performance 5PB1104 Datasheet 1:4 LVCMOS Clock Buffer Description Features High-performance 1:4 LVCMOS clock buffer The 5PB1104 is a high-performance LVCMOS clock buffer. It has an additive phase jitter of 50fs RMS. Very low pin-to-pin skew: < 50ps Very low additive jitter: < 50fs The 5PB1104 also supports a synchronous glitch-free output enable (OE) function to eliminate any potential intermediate Supply voltage: 1.8V to 3.3V incorrect output clock cycles when enabling or disabling outputs. It 3.3V tolerant input clock can operate from a 1.8V to 3.3V supply. f = 200MHz MAX Integrated serial termination for 50 channel Typical Applications 2.0 2.0 mm 8-VFQFN package Automotive applications AEC-Q100 Grade 1 (-40C to +125C) and Grade 2 (-40C to +105C) Block Diagram LVCMOS LVCMOS CLKIN Y0 LVCMOS Y1 LVCMOS Y2 LVCMOS Y3 1G 2018 Integrated Device Technology, Inc. 1 October 15, 20185PB1104 Datasheet Pin Assignments Figure 1. Pin Assignments for 2.0 2.0 mm 8-VFQFN Package Top View Y1 CLKIN 1 8 1G 2 7 Y3 5PB1104 Y0 3 6 VDD Y2 GND45 Pin Descriptions Table 1. Pin Descriptions Number Name Type Description 1 CLKIN Input LVCMOS clock input. 2 1G Input Clock output enable. 3Y0 LVCMOS clock output. Output Power 4 GND Connect to ground. 5Y2 LVCMOS clock output. Output 6V Power 1.8V to 3.3V power supply. DD 7Y3 Output LVCMOS clock output. 8Y1 Output LVCMOS clock output. Output Logic Table Inputs Output CLKIN 1G Yn XL L LHL HH H After at least three cycles of input clock toggling. Output Enable function is asynchronous to eliminate any intermediate incorrect output clock cycles during transition which may cause frequency peaking to the downstream device. 2018 Integrated Device Technology, Inc. 2 October 15, 2018