Product Information

6116SA15SOG

6116SA15SOG electronic component of Renesas

Datasheet
SRAM 16K Asynch. 2Kx8 HS, L-Pwr, SRAM

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 9.4995 ea
Line Total: USD 9.4995

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Wed. 10 Apr to Fri. 12 Apr

MOQ : 1
Multiples : 1

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6116SA15SOG
Renesas

1 : USD 7.7722
10 : USD 6.5666
25 : USD 6.5181
50 : USD 6.4696
100 : USD 5.6642
250 : USD 5.6409
500 : USD 5.3734

     
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RoHS - XON
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CMOS Static RAM 6116SA 16K (2K x 8-Bit) 6116LA Features Description High-speed access and chip select times The IDT6116SA/LA is a 16,384-bit high-speed static RAM organized Commercial: 15/20/25ns (max.) as 2K x 8. It is fabricated using high-performance, high-reliability CMOS Industrial: 20/25ns (max.) technology. Military: 20/25/35/45/55/70/90/120/150ns (max.) Access times as fast as 15ns are available. The circuit also offers a Low-power consumption reduced power standby mode. When CS goes HIGH, the circuit will Battery backup operation automatically go to, and remain in, a standby power mode, as long as CS 2V data retention voltage (LA version only) remains HIGH. This capability provides significant system level power and Produced with advanced CMOS high-performance cooling savings. The low-power (LA) version also offers a battery backup technology data retention capability where the circuit typically consumes only 1W to CMOS process virtually eliminates alpha particle soft-error 4W operating off a 2V battery. rates All inputs and outputs of the IDT6116SA/LA are TTL-compatible. Fully Input and output directly TTL-compatible static asynchronous circuitry is used, requiring no clocks or refreshing for Static operation: no clocks or refresh required operation. Available in ceramic 24-pin DIP, ceramic and plastic 24-pin Thin The IDT6116SA/LA is packaged in 24-pin 300mil plastic DIP, 24-pin Dip and 24-pin SOIC 600mil and 300mil ceramic DIP, or 24-lead gull-wing SOIC providing high Military product compliant to MIL-STD-833, Class B board-level packing densities. Industrial temperature range (40C to +85C) is available Military grade product is manufactured in compliance to MIL-STD-883, for selected speeds Class B, making it ideally suited to military temperature applications Green parts available, see ordering information demanding the highest level of performance and reliability. Functional Block Diagram A0 CC V 128 X 128 ADDRESS MEMORY GND DECODER ARRAY A10 I/O0 I/O CONTROL INPUT DATA CIRCUIT I/O7 , CS CONTROL OE CIRCUIT WE 3089 drw 01 1 Jul.17.206116SA/LA CMOS Static RAM 2K (16K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges (1) Pin Configurations Capacitance (TA = +25C, f = 1.0 MHZ) (1) Symbol Parameter Conditions Max. Unit 7 VCC CIN Input Capacitance VIN = 0V 8 pF A 1 24 6 A8 A 2 23 CI/O I/O Capacitance VOUT = 0V 8 pF 5 A 3 A9 22 A4 4 PTG24 21 WE 3089 tbl 03 NOTE: CD24 A 3 20 OE 5 1. This parameter is determined by device characterization, but is not production 2 SD24 A 19 A10 6 tested. PSG24 1 A 7 18 CS 0 A 8 17 I/O7 0 I/O 9 16 I/O6 I/O 1 5 10 15 I/O I/O 2 I/O 11 14 4 13 GND 12 I/O 3 (1) Absolute Maximum Ratings 3089 drw 02 Symbol Rating Com l. Mil. Unit DIP/SOIC (2) VTERM Terminal Voltage -0.5 to +7.0 -0.5 to +7.0 V with Respect Top View to GND o Operating 0 to +70 -55 to +125 C TA Temperature NOTE: 1. This text does not indicate orientation of actual part-marking. o Temperature -55 to +125 -65 to +135 C TBIAS Under Bias o TSTG Storage Temperature -55 to +125 -65 to +150 C Pin Description PT Power Dissipation 1.0 1.0 W Name Description IOUT DC Output Current 50 50 mA 3089 tbl 04 A0 - A10 Address Inputs NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS I/O0 - I/O7 Data Input/Output may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those Chip Select CS indicated in the operational sections of this specification is not implied. Exposure Write Enable to absolute maximum rating conditions for extended periods may affect WE reliability. OE Output Enable 2. VTERM must not exceed VCC +0.5V. VCC Power GND Ground 3089 tbl 01 (1) Truth Table Mode CS OE WE I/O Standby H X X High-Z Read L L H DATAOUT Read L H H High-Z Write L X L DATAIN 3089 tbl 02 NOTE: 1. H = VIH, L = VIL, X = Don t Care. 2 Jul.17.20

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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