DATASHEET LOW SKEW 1 TO 4 CLOCK BUFFER ICS651 Description Features The ICS651 is a low skew, single input to four output, clock Low skew outputs (250 ps) TM buffer. Part of IDTs ClockBlocks family, this is a low Packaged in 8-pin SOIC skew, small clock buffer. RoHS 6 compliant package IDT makes many non-PLL and PLL based low skew output Low power CMOS technology devices as well as Zero Delay Buffers to synchronize Operating Voltages of 1.5 V to 2.5 V clocks. Contact us for all of your clocking needs. Output Enable pin tri-states outputs 3.3 V tolerant input clock Industrial or commercial temperature ranges Block Diagram Q0 Q1 ICLK Q2 Q3 Output Enable IDT LOW SKEW 1 TO 4 CLOCK BUFFER 1 ICS651 REV H 101111ICS651 LOW SKEW 1 TO 4 CLOCK BUFFER FAN OUT BUFFER Pin Assignment ICLK 1 8 OE VDD Q1 2 7 Q2 3 6 GND Q3 5 Q4 4 Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK Input Clock Input. 3.3 V tolerant input. 2 Q1 Output Clock Output 1. 3 Q2 Output Clock Output 2. 4 Q3 Output Clock Output 3. 5 Q4 Output Clock Output 4. 6 GND Power Connect to ground. 7 VDD Power Connect to +1.5 V or +2.5 V. 8 OE Input Output Enable. Tri-states outputs when low. Connect to VDD for normal operation. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 F should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the ICS651 is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15 ps of skew. IDT LOW SKEW 1 TO 4 CLOCK BUFFER 2 ICS651 REV H 101111