HIGH-SPEED IDT7025S/L 8K x 16 DUAL-PORT STATIC RAM LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 IDT7025 easily expands data bus width to 32 bits or more Features using the Master/Slave select when cascading more than True Dual-Ported memory cells which allow simultaneous one device reads of the same memory location M/S = H for BUSY output flag on Master High-speed access M/S = L for BUSY input on Slave Military: 20/25/35/55/70ns (max.) Interrupt Flag Industrial: 55ns (max.) On-chip port arbitration logic Commercial: 15/17/20/25/35/55ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT7025S Fully asynchronous operation from either port Active: 750mW (typ.) Battery backup operation2V data retention Standby: 5mW (typ.) TTL-compatible, single 5V (10%) power supply IDT7025L Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin Active: 750mW (typ.) Quad Flatpack Standby: 1mW (typ.) Industrial temperature range (40C to +85C) is available Separate upper-byte and lower-byte control for multiplexed for selected speeds bus compatibility Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBR UBL LBL LBR CEL CER OEL OER I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0R-I/O7R I/O0L-I/O7L (1,2) (1,2) BUSYR BUSYL A12R A12L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 13 13 ARBITRATION CEL INTERRUPT CER SEMAPHORE OEL OER LOGIC R/WL R/WR SEML SEMR (2) (2) INTR M/S INTL 2683 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. MARCH 2018 1 DSC 2683/12 2018 Integrated Device Technology, Inc.IDT7025S/L High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges feature controlled by Chip Enable (CE) permits the on-chip circuitry of each Description port to enter a very low standby power mode. The IDT7025 is a high-speed 8K x 16 Dual-Port Static RAM. The Fabricated using IDTs CMOS high-performance technology, these IDT7025 is designed to be used as a stand-alone 128K-bit Dual-Port RAM devices typically operate on only 750mW of power. Low-power (L) or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more versions offer battery backup data retention capability with typical power word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach consumption of 500W from a 2V battery. in 32-bit or wider memory system applications results in full-speed, error- The IDT7025 is packaged in a ceramic 84-pin PGA, an 84-pin free operation without the need for additional discrete logic. Flatpack, PLCC, and a 100-pin TQFP. Military grade product is manu- This device provides two independent ports with separate control, factured in compliance with the latest revision of MIL-PRF-38535 QML, address, and I/O pins that permit independent, asynchronous access for making it ideally suited to military temperature applications demanding the reads or writes to any location in memory. An automatic power down highest level of performance and reliability. (1,2,3) Pin Configurations INDEX 11/06/01 1110 9876543218483 82 81 80 79 78 77 76 75 I/O8L 74 A7L 12 A6L I/O9L 73 13 A5L I/O10L 72 14 A4L I/O11L 15 71 A3L I/O12L 16 70 A2L I/O13L 69 17 A1L GND 68 18 A0L I/O14L IDT7025J or F 67 19 (4) J84-1 INTL I/O15L 66 20 (4) F84-2 BUSYL VCC 21 65 84-Pin PLCC/Flatpack GND GND 22 64 (5) Top View I/O0R 63 M/S 23 I/O1R 62 BUSYR 24 I/O2R 61 25 INTR VCC 60 26 A0R I/O3R 27 59 A1R I/O4R 28 58 A2R I/O5R 29 57 A3R I/O6R 56 A4R 30 I/O7R 55 A5R 31 I/O8R 54 A6R 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 2683 drw 02 Index 11/06/01 1009998 97 9695 94 93 92 9190 8988 87 86 8584 8382 81 80 79 78 77 76 1 N/C N/C 75 2 N/C 74 N/C 3 N/C 73 N/C 4 N/C 72 N/C 5 I/O10L 71 A5L I/O11L 6 70 A4L 7 I/O12L 69 A3L 8 68 A2L I/O13L 9 GND 67 A1L 10 66 A0L I/O14L IDT7025PF (4) I/O15L 11 PN100-1 65 INTL 12 64 VCC BUSYL 100-Pin TQFP GND 13 63 GND (5) Top View 14 62 I/O0R M/S I/O1R 15 61 BUSYR 16 60 I/O2R INTR 17 59 A0R VCC NOTES: 58 I/O3R 18 A1R 19 57 A2R 1. All VCC pins must be connected to power supply. I/O4R I/O5R 20 56 A3R 2. All GND pins must be connected to ground supply. 21 55 I/O6R A4R 3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in. 22 54 N/C N/C F84-2 package body is approximately 1.17 in x 1.17 in x .11 in. 53 N/C 23 N/C 24 52 N/C PN100-1 package body is approximately 14mm x 14mm x 1.4mm. N/C 51 N/C 25 N/C 4. This package code is used to reference the package diagram. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5. This text does not indicate orientation of the actual part-marking 2683 drw 03 6.422 I/O9R I/O7L I/O10R I/O6L I/O11R I/O5L I/O12R I/O4L I/O13R I/O3L I/O14R I/O2L GND GND I/O15R I/O1L OER I/O0L /WR R OEL GND VCC SEMR R/WL CER SEML UBR CEL LBR UBL A12R LBL A11R A12L A10R A11L A9R A10L A8R A9L A7R A8L I/O7R I/O9L I/O8R I/O8L I/O9R I/O7L I/O10R I/O6L I/O5L I/O11R I/O12R I/O4L I/O3L I/O13R I/O14R I/O2L GND GND I/O15R I/O1L OER I/O0L R/WR OEL GND VCC R/WL SEMR ER SEML C CEL UBR BR UBL L LBL A12R A12L A11R A10R A11L A10L A9R A8R A9L A8L A7R A6R A7L A6L A5R