70V25L25PFGI Renesas

HIGH-SPEED 3.3V 70V35/34S/L 8/4K x 18 DUAL-PORT 70V25/24S/L 8/4K x 16 DUAL-PORT STATIC RAM Features IDT70V25/24S IDT70V25/24L Active: 400mW (typ.) Active: 380mW (typ.) True Dual-Ported memory cells which allow simultaneous reads of the same memory location Standby: 3.3mW (typ.) Standby: 660W (typ.) High-speed access Separate upper-byte and lower-byte control for multiplexed IDT70V35 bus compatibility IDT70V35/34 (IDT70V25/24) easily expands data bus width Commercial: 15ns (max.) to 36 bits (32 bits) or more using the Master/Slave select Industrial: 20ns IDT70V34 when cascading more than one device Commercial: 15ns (max.) M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave IDT70V25 BUSY and Interrupt Flag Commercial: 15/35ns (max.) Industrial: 20/25ns On-chip port arbitration logic IDT70V24 Full on-chip hardware support of semaphore signaling between ports Commercial: 15//35/55ns (max.) Fully asynchronous operation from either port Industrial: 15/20ns Low-power operation LVTTL-compatible, single 3.3V (0.3V) power supply IDT70V35/34L Available in a 100-pin TQFP (IDT70V35/34) & (IDT70V25/24), and 84-pin PLCC (IDT70V24) Active: 415mW (typ.) Industrial temperature range (-40C to +85C) is available Standby: 660W (typ.) for selected speeds Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBL UBR LBL LBR CER CEL OEL OER , (5) (5) I/O9R-I/O17R I/O9L-I/O17L I/O I/O Control Control (4) (4) I/O0R-I/O8R I/O0L-I/O8L (2,3) (2,3) BUSYR BUSYL (1) (1) A12R A12L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 13 13 ARBITRATION INTERRUPT CER CEL SEMAPHORE OEL OER LOGIC R/WL R/WR SEMR SEML (3) (3) INTR M/S NOTES: INTL 5624 drw 01 1. A12 is a NC for IDT70V34 and for IDT70V24. 2. (MASTER): BUSY is output (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull. 4. I/O0x - I/O7x for IDT70V25/24. 5. I/O8x - I/O15x for IDT70V25/24. OCTOBER 2019 1 DSC-5624/10 2019 Integrated Device Technology, Inc.70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70V35/34 (IDT70V25/24) is a high-speed 8/4K x 18 (8/4K feature controlled by CE permits the on-chip circuitry of each port to enter x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is de- a very low standby power mode. signed to be used as a stand-alone Dual-Port RAM or as a combination Fabricated using CMOS high-performance technology, these de- MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory vices typically operate on only 430mW (IDT70V35/34) and 400mW system applications results in full-speed, error-free operation without the (IDT70V25/24) of power. need for additional discrete logic. The IDT70V35/34 (IDT70V25/24) is packaged in a plastic 100-pin This device provides two independent ports with separate control, Thin Quad Flatpack. The IDT70V24 is packaged in a 84-Pin PLCC. address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down (1,2,3,4) Pin Configurations 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A5R A6L 76 50 A6R A7L 77 49 A7R A8L 78 48 47 A8R 79 A9L 80 46 A9R A10L 45 81 A10R A11L (1) A12L 82 44 A11R (1) LBL 43 A12R 83 UBL 84 42 LBR UBR CEL 85 41 CER SEML 86 40 70V35/34 R/WL 87 39 SEMR (5) PNG100 Vss VDD 38 88 OEL 89 R/WR 37 100-Pin TQFP I/O0L 36 90 OER Top View I/O1L 91 35 I/O16R Vss 92 34 Vss I/O2L 93 I/O15R 33 I/O3L 94 32 I/O14R I/O4L 95 I/O13R 31 I/O5L 96 I/O12R 30 97 I/O6L 29 I/O11R 98 I/O7L I/O10R 28 I/O9L 99 27 I/O9R I/O10L 100 26 I/O7R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5624 drw 02 NOTES: 1. A12 is a NC for IDT70V34. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. PNG100 package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6.422 N/C N/C N/C N/C I/O8L N/C I/O17L N/C I/O11L A5L I/O12L A4L I/O13L A3L I/O14L A2L Vss A1L I/O15L A0L I/O16L INTL VDD BUSYL Vss Vss I/O0R M/S I/O1R BUSYR I/O2R INTR VDD A0R I/O3R A1R I/O4R A2R I/O5R A3R I/O6R A4R I/O8R N/C I/O17R N/C N/C N/C N/C N/C