IDT7130SA/LA
HIGH SPEED
IDT7140SA/LA
1K X 8 DUAL-PORT
STATIC SRAM
Features
On-chip port arbitration logic (IDT7130 Only)
High-speed access
BUSY output flag on IDT7130; BUSY input on IDT7140
Commercial: 20/25/35/55/100ns (max.)
Industrial: 25/55/100ns (max.) INT flag for port-to-port communication
Fully asynchronous operation from either port
Military: 25/35/55/100ns (max.)
Battery backup operation2V data retention (LA only)
Low-power operation
IDT7130/IDT7140SA TTL-compatible, single 5V 10% power supply
Military product compliant to MIL-PRF-38535 QML
Active: 550mW (typ.)
Standby: 5mW (typ.) Industrial temperature range (40C to +85C) is available
IDT7130/IDT7140LA for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
Active: 550mW (typ.)
Standby: 1mW (typ.) PLCC, and 64-pin STQFP and TQFP
MASTER IDT7130 easily expands data bus width to 16-or- Green parts available, see ordering information
more-bits using SLAVE IDT7140
Functional Block Diagram
OER
OEL
CEL
CER
R/WL R/WR
,
I/O0L-I/O7L
I/O0R-I/O7R
I/O I/O
Control Control
(1,2)
(1,2)
BUSYL BUSYR
A9L
A9R
Address MEMORY Address
Decoder ARRAY Decoder
A0L A0R
10
10
ARBITRATION
CEL and
CER
INTERRUPT
OEL OER
LOGIC
R/WR
R/WL
(2) (2)
INTR
INTL
2689 drw 01
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
JANUARY 2013
1
2013 Integrated Device Technology, Inc. DSC-2689/15 IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Description
of each port to enter a very low standby power mode.
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 550mW of power. Low-power (LA)
Dual-Port RAM or as aMASTE Dual-Port RAM together with the
versions offer battery backup data retention capability, with each Dual-
IDT7140SLAV Dual-Port in 16-bit-or-more word width systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or- Port typically consuming 200W from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze
more-bit memory system applications results in full-speed, error-
or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP
free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate con- and STQFP. Military grade products are manufactured in compli-
ance with the latest revision of MIL-PRF-38535 QML, making it
trol, address, and I/O pins that permit independent asynchronous
access for reads or writes to any location in memory. An automatic ideally suited to military temperature applications demanding the
power down feature, controlled by CE, permits the on chip circuitry highest level of performance and reliability.
(1,2,3)
Pin Configurations
01/08/02
INDEX
65 43 2 48 47 46 45 44 43
1
7 42
A0R
A1L
8 41
A2L A1R
9 40 A2R
A3L
10 39
A3R
A4L
IDT7130/40L48 or F
(4)
11 38
L48-1
A5L A4R
&
12 37
A6L A5R
(4)
F48-1
13 36
A7L A6R
48-Pin LCC/ Flatpack
14 35
A8L (5) A7R
Top View
15 34
A9L A8R
16 33
I/O0L A9R
17 32
I/O1L I/O7R
18 31
I/O2L I/O6R
19 20 21 22 23 24 25 26 27 28 29 30
,
2689 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
A0L
I/O3L
EL
O
I/O4L
INTL
I/O5L
BUSYL
I/O6L
I/O7L R/WL
CEL
GND
VCC
I/O0R
CER
I/O1R
R/WR
I/O2R
BUSYR
I/O3R
INTR
I/O4R
OER
I/O5R