71V016SA15PHGI8 Renesas

71V016SA 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Features Description 64K x 16 advanced high-speed CMOS Static RAM The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized Equal access and cycle times as 64K x 16. It is fabricated using high-performance, high-reliability CMOS Commercial: 10/12/15/20ns technology. This state-of-the-art technology, combined with innovative Industrial: 10/12/15/20ns circuit design techniques, provides a cost-effective solution for high-speed One Chip Select plus one Output Enable pin memory needs. Bidirectional data inputs and outputs directly The IDT71V016 has an output enable pin which operates as fast as LVTTL-compatible 5ns, with address access times as fast as 10ns. All bidirectional inputs and Low power consumption via chip deselect outputs of the IDT71V016 are LVTTL compatible and operation is from a Upper and Lower Byte Enable Pins single 3.3V supply. Fully static asynchronous circuitry is used, requiring Single 3.3V power supply no clocks or refresh for operation. Available in 44-pin Plastic SOJ, 44-pin TSOP, and The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ, 48-Ball Plastic FBGA packages a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA. Industrial temperature range (40C to +85C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram Output OE Enable Buffer Address Row / Column A0 A15 Buffers Decoders I/O15 High 8 8 Chip Byte CS Enable I/O Buffer Buffer I/O8 Sense 16 64K x 16 Amps and Memory Write Array Write Drivers WE Enable I/O7 Buffer Low 8 8 Byte I/O Buffer I/O0 BHE Byte Enable Buffers BLE 3834 drw 01 1 Jun.23.2071V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges (1) 1 2 3 456 Pin Configurations - PBG44, PHG44 A A0 A1 A2 NC BLE OE A4 1 44 A5 A3 2 A6 43 BI/O8 A3 A4 I/O0 BHE CS A2 3 42 A7 A1 4 OE 41 CI/O9 I/O10 A5 A6 I/O1 I/O2 A0 5 BHE 40 CS 6 BLE 39 I/O0 7 38 I/O15 DVSS I/O11 NC A7 I/O3 VDD I/O1 8 I/O14 37 71V016SA I/O2 9 36 I/O13 EVDD I/O12 NC NC I/O4 VSS PBG44 I/O3 10 I/O12 35 PHG44 VDD 11 34 VSS FI/O14 I/O13 A14 A15 I/O5 I/O6 VSS 12 VDD 33 I/O4 13 32 I/O11 G I/O15 NC A12 A13 I/O7 WE I/O5 14 I/O10 31 I/O6 15 30 I/O9 I/O7 16 I/O8 29 HNC A8 A9 A10 A11 NC WE NC 17 28 3834 tbl 02a A15 18 A8 (1) 27 FBGA (BF48, BFG48) A14 A9 19 26 Top View A13 A10 20 25 NOTE: A12 A11 21 24 1. This text does not indicate orientation of actual part-marking. NC NC 22 23 Pin Description A0 A15 Address Inputs Input 3834 drw 02 SOJ/TSOP CS Chip Select Input Top View Write Enable Input WE NOTE: OE Output Enable Input 1. This text does not indicate orientation of actual part-marking. BHE High Byte Enable Input BLE Low Byte Enable Input I/O0 I/O15 Data Input/Output I/O VDD 3.3V Power Power VSS Ground Gnd (1) 3834 tbl 01 Truth Table CS OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 Function H X X X X High-Z High-Z Deselected Standby LL H L H DATAOUT High-Z Low Byte Read L L H H L High-Z DATAOUT High Byte Read LL H L L DATAOUT DATAOUT Word Read LX L L L DATAIN DATAIN Word Write LX L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled 3834 tbl 02 NOTE: 1. H = VIH, L = VIL, X = Don t care. 2 Jun.23.20