3.3V CMOS Static RAM IDT71V424S IDT71V424L 4 Meg (512K x 8-Bit) Features Description 512K x 8 advanced high-speed CMOS Static RAM The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized JEDEC Center Power / GND pinout for reduced noise as 512K x 8. It is fabricated using high-perfomance, high-reliability CMOS Equal access and cycle times technology. This state-of-the-art technology, combined with innovative Commercial and Industrial: 10/12/15ns circuit design techniques, provides a cost-effective solution for high-speed Single 3.3V power supply memory needs. One Chip Select plus one Output Enable pin The IDT71V424 has an output enable pin which operates as fast as Bidirectional data inputs and outputs directly 5ns, with address access times as fast as 10ns. All bidirectional inputs and TTL-compatible outputs of the IDT71V424 are TTL-compatible and operation is from a Low power consumption via chip deselect single 3.3V supply. Fully static asynchronous circuitry is used, requiring Available in 36-pin, 400 mil plastic SOJ package and no clocks or refresh for operation. 44-pin, 400 mil TSOP. The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44- pin, 400 mil TSOP. Functional Block Diagram A0 4,194,304-BIT ADDRESS MEMORY ARRAY DECODER A18 8 8 I/O0-I/O7 I/O CONTROL 8 WE CONTROL OE LOGIC CS 3622 drw 01 SEPTEMBER 2013 1 2013 Integrated Device Technology, Inc. DSC-3622/10IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges Pin Configuration Pin Configuration NC NC 1 44 A0 1 36 NC NC 2 NC 43 A1 2 35 A18 A0 3 NC 42 A2 3 34 A17 A18 A1 4 41 A3 4 33 A16 A17 A4 5 32 A15 A2 5 40 CS OE A16 6 31 A3 6 39 I/O 0 7 30 I/O 7 A4 7 38 A15 I/O 1 8 29 I/O 6 8 37 CS OE SO36-1 VDD 9 28 VSS I/00 9 36 I/07 VSS 10 27 VDD I/01 10 35 I/06 I/O 2 11 26 I/O 5 SO44-2 I/O 3 12 25 I/O 4 VDD 11 34 VSS WE 13 24 A14 VSS 12 33 VDD A5 14 23 A13 I/02 13 32 I/05 A6 15 22 A12 I/03 14 31 I/04 A7 16 21 A11 A14 15 30 WE A8 17 20 A10 A5 16 29 A13 A9 18 19 NC A6 17 28 A12 A7 18 27 A11 3622 drw 02 SOJ A8 19 26 A10 Top View NC A9 20 25 NC NC 21 24 NC NC 22 23 3622 drw 11 TSOP Top View Pin Description Capacitance (TA = +25C, f = 1.0MHz, SOJ package) A0 A18 Address Inputs Input (1) Symbol Parameter Conditions Max. Unit Chip Select Input CS CIN Input Capacitance VIN = 3dV 7 pF WE Write Enable Input CI/O I/O Capacitance VOUT = 3dV 8 pF OE Output Enable Input 3622 tbl 03 I/O0 - I/O7 Data Input/Output I/O NOTE: 1. This parameter is guaranteed by device characterization, but not production VDD 3.3V Power Power tested. VSS Ground Gnd 3622 tbl 02 (1,2) Truth Table CS OE WE I/O Function OUT Read Data LL H DATA LX L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected - Standby (ISB) (3) X X High-Z Deselected - Standby (ISB1) VHC 3622 tbl 01 NOTES: 1. H = VIH, L = VIL, x = Don t care. 2. VLC = 0.2V, VHC = VDD -0.2V. 3. Other inputs VHC or VLC. 6.422