72255LA15PFG

CMOS SuperSync FIFO 8,192 x 18 IDT72255LA 16,384 x 18 IDT72265LA Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- FEATURES pin Slim Thin Quad Flat Pack (STQFP) Choose among the following memory organizations: High-performance submicron CMOS technology IDT72255LA 8,192 x 18 Industrial temperature range (40C to +85C) is available IDT72265LA 16,384 x 18 Green parts available, see ordering information Pin-compatible with the IDT72275/72285 SuperSync FIFOs 10ns read/write cycle time (8ns access time) DESCRIPTION Fixed, low first word data latency time Auto power down minimizes standby power consumption The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS Master Reset clears entire FIFO First-In-First-Out (FIFO) memories with clocked read and write controls. These Partial Reset clears data, but retains programmable settings FIFOs offer numerous improvements over previous SuperSync FIFOs, Retransmit operation with fixed, low first word data latency time including the following: Empty, Full and Half-Full flags signal FIFO status The limitation of the frequency of one clock input with respect to the other has Programmable Almost-Empty and Almost-Full flags, each flag been removed. The Frequency Select pin (FS) has been removed, thus can default to one of two preselected offsets it is no longer necessary to select which of the two clock inputs, RCLK or Program partial flags by either serial or parallel means WCLK, is running at the higher frequency. Select IDT Standard timing (using EF and FF flags) or First The period required by the retransmit operation is now fixed and short. Word Fall Through timing (using OR and IR flags) The first word data latency period, from the time the first word is written to an Output enable puts data outputs into high impedance state empty FIFO to the time it can be read, is now fixed and short. (The variable Easily expandable in depth and width clock cycle counting delay associated with the latency period found on Independent Read and Write clocks (permit reading and writing previous SuperSync devices has been eliminated on this SuperSync family.) simultaneously) FUNCTIONAL BLOCK DIAGRAM D0 -D17 WEN WCLK LD SEN OFFSET REGISTER INPUT REGISTER FF /IR PAF FLAG EF /OR WRITE CONTROL LOGIC PAE LOGIC HF FWFT/SI RAM ARRAY 8,192 x 18 16,384 x 18 WRITE POINTER READ POINTER READ CONTROL RT LOGIC OUTPUT REGISTER MRS RESET RCLK LOGIC PRS REN 4670 drw01 Q0 -Q17 OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync FIFO is a trademark of Integrated Device Technology, Inc JULY 2014 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4670/4IDT72255LA/72265LA CMOS SuperSync FIFO COMMERCIAL AND INDUSTRIAL 8,192 x 18 and 16,384 x 18 TEMPERATURE RANGES The frequencies of both the RCLK and the WCLK signals may vary from 0 DESCRIPTION (CONTINUED) to fMAX with complete independence. There are no restrictions on the frequency SuperSync FIFOs are particularly appropriate for networking, video, of one clock input with respect to the other. telecommunications, data communications and other applications that need to There are two possible timing modes of operation with these devices: IDT buffer large amounts of data. Standard mode and First Word Fall Through (FWFT) mode. The input port is controlled by a Write Clock (WCLK) input and a Write Enable In IDT Standard mode, the first word written to an empty FIFO will not appear (WEN) input. Data is written into the FIFO on every rising edge of WCLK when on the data output lines unless a specific read operation is performed. A read WEN is asserted. The output port is controlled by a Read Clock (RCLK) input operation, which consists of activating REN and enabling a rising RCLK edge, and Read Enable (REN) input. Data is read from the FIFO on every rising edge will shift the word from internal memory to the data output lines. of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-state control of the outputs. PIN CONFIGURATIONS PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 WEN Q17 2 47 SEN Q16 3 46 DC GND VCC 4 45 Q15 5 44 GND Q14 D17 6 43 VCC D16 7 42 Q13 D15 8 41 Q12 D14 9 40 Q11 D13 GND 10 39 D12 11 38 Q10 D11 Q9 12 37 D10 Q8 13 36 D9 Q7 14 35 D8 Q6 15 34 D7 GND 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4670 drw02 TQFP (PN64, ORDER CODE: PF) STQFP (PP64, ORDER CODE: TF) TOP VIEW NOTE: 1. DC = Dont Care. Must be tied to GND or VCC, cannot be left open. 2 WCLK PRS D5 MRS D4 D3 LD D2 FWFT/SI D1 GND D0 FF/IR GND PAF Q0 HF Q1 VCC PAE GND EF/OR Q2 RCLK Q3 REN VCC RT Q4 Q5 OE D6