nOE Differential Clock/Data Multiplexer ICS831721I DATASHEET General Description Features The ICS831721I is a high-performance, differential HCSL clock/data 2:1 differential clock/data multiplexer with fanout multiplexer and fanout buffer.The device is designed for the Two selectable, differential inputs multiplexingofhigh-frequencyclockanddatasignals.Thedevicehas Each differential input pair can accept the following levels: HCSL, two differential, selectable clock/data inputs.The selected input LVHSTL, LVDS and LVPECL signal is output at one differential HCSL output. Each input pair accepts HCSL, LVDS, and LVPECL levels.The ICS831721I is One differential HCSL output characterized to operate from a 3.3V power supply. Guaranteed Maximum input/output clock frequency: 700MHz (maximum) input, output-to-output and part-to-part skew characteristics make Maximum input/output data rate: 1400Mb/s (NRZ)LVCMOS the ICS831721I ideal for those clock and data distribution interface levels for all control inputs applications demanding well-defined performance and repeatability. The ICS831721I supports the clock multiplexing and distribution of Input skew: 55ps (maximum) PCI Express Generation 1, 2 and 3 clock signals. Part-to-part skew: 400ps (maximum) Full 3.3V supply voltage Available in lead-free (RoHS 6) 16TSSOP package -40C to 85C ambient operating temperature Block Diagram Pin Assignment CLK0 1 16 IREF nCLK0 2 15 SEL IREF VDD 3 14 VDD CLK1 4 13 nQ nCLK1 5 12 Q Pulldown CLK0 6 GND 11 VDD Pullup/down 0 nCLK0 nc 7 10 GND Q VDD 8 9 nQ Pulldown CLK1 1 Pullup/down nCLK1 ICS831721I 16-LeadTSSOP Pulldown 4.4mm x 5.0mm x 0.925mm package body SEL Pullup/down nOE G Package TopView ICS831721AGI REVISION A FEBRUARY 3, 2014 1 2014 Integrated Device Technology, Inc.ICS831721I Data Sheet DIFFERENTIAL CLOCK/DATA MULTIPLEXER Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 CLK0 Input Pulldown Non-inverting clock/data input 0. 2 nCLK0 Input Pullup/Pulldown Inverting differential clock input 0. V /2 default when left floating. DD Power 3, 8, 11, 14 V Positive power supply. DD 4 CLK1 Input Pulldown Non-inverting clock/data input 1. 5 nCLK1 Input Pullup/Pulldown /2 default when left floating. Inverting differential clock input 1. V DD 6, 10 GND Power Power supply ground. 7 nc Unused No connect. 9 nOE Input Pullup Output enable. See Table 3A for function. LVCMOS/LVTTL interface levels. 12, 13 Q, nQ Output Differential output pair. HCSL interface levels. 15 SEL Input Pulldown Input select. See Table 3B for function. LVCMOS/LVTTL interface levels. An external fixed precision resistor (475) from this pin to ground provides a 16 IREF Input reference current used for the differential current-mode Q, nQ outputs. NOTE: Pullup and pulldown refer to internal input resistors. SeeTable 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4 pF C IN Input Pulldown Resistor 51 k R PULLDOWN Input Pullup Resistor 51 k R PULLUP Function Tables Table 3A. nOE ConfigurationTable Table 3B. SEL ConfigurationTable Input Input nOE Operation SEL Selected Input 0 Output Q, nQ is enabled. 0 (default) CLK0, nCLK0 1 (default) Output Q, nQ is in a high-impedance state. 1 CLK1, nCLK1 NOTE: nOE is an asynchronous control. NOTE: SEL is an asynchronous control. ICS831721AGI REVISION A FEBRUARY 3, 2014 2 2014 Integrated Device Technology, Inc.