PRELIMINARY
FEMTOCLOCKS VCXO BASED ICS843002-31
FREQUENCY TRANSLATOR/JITTER ATTENUATOR
GENERAL DESCRIPTION FEATURES
The ICS843002-31 is a member of the
Outputs:
ICS
HiperClockS family of high performance clock
Two high frequency differential LVPECL outputs
HiPerClockS
solutions from IDT. This monolithic device is a high-
Output frequency: up to 700MHz
performance, PLL-based synchronous clock
One LVCMOS/LVTTL VCXO PLL output with output enable
generator and jitter attenuation circuit. The
One Reference clock output with output enable
ICS843002-31 contains two clock multiplication stages that are
cascaded in series. The first stage is a VCXO-based PLL that
One LOCK detect output
is optimized to provide reference clock jitter attenuation, to be
Input mux supports 3 selectable inputs: one differential input
jitter tolerant, and to provide a stable reference clock for the
second multiplication stage. The second stage is the proprietary pair and two LVCMOS/LVTTL input clocks
IDT FemtoClock circuit which is a high-frequency, sub-
13-bit VCXO PLL feedback and reference dividers provide
picosecond clock multiplier.
wide range of frequency translation ratio options
FemtoClock frequency multiplier supports rate of:
The VCXO PLL has an on-chip VCXO circuit that uses an
560MHz - 700MHz
external, inexpensive pullable crystal in the 17.5 to 25MHz
range. The PLL includes 13 bit reference and feedback
Lock Detect output reports lock status of VCXO PLL
dividers supporting complex PLL multiplication ratios and
VCXO PLL circuit provides jitter attenuation with
input reference clock rates as low as 2.3kHz. External loop
loop bandwidth of 250Hz and below (user adjustable)
filter components are used (two resistors and two capacitors)
to achieve the low loop bandwidth needed for jitter atten-
RMS phase jitter, random at 12kHz to 20MHz:
uation of a recovered data clock.
<1ps (design target)
The FemtoClock circuit can multiply the VCXO crystal frequency
3.3V supply voltage
by a factor of 28 or 32 (selectable) and provide a clock output of
0C to 70C ambient operating temperature
up to 700MHz.
Industrial temperature information available upon request
Clock Input/Output Configuration:
Available in both standard (RoHS 5) and lead-free (RoHS 6)
Clock Inputs - one differential pair, two singled ended
packages
(mux selected)
Differential input pair can support LVPECL, LVDS,
PIN ASSIGNMENT
LVHSTL, SSTL, HCSL or single-ended LVCMOS
or LVTTL levels
Singled ended inputs can support LVCMOS or
LVTTL levels
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Clock Outputs, FemtoClockS two LVPECL pairs
LF1 1 48 VEE
(selectable output dividers)
LF0 2 47 REF_CLK
Clock Output, VCXO one single ended output ISET 3 46 VCLK
VEE 4 45 LOCK
(at VCXO crystal frequency)
NV1 5 44 VCCO_CMOS
Clock Output, other VCXO reference clock
NV0 6 43 nQB
ICS843002-31
VCC 7 42 QB
64-Lead TQFP, EPAD
MR 8 41 VEE
Example Applications:
10mm x 10mm x 1.0mm
CLK0 9 40 nQA
SONET/SDH line card clock generator (up to 622.08MHz package body
nCLK0 10 39 QA
for OC-48) using 8kHz frame clock as input reference Y package
11
OE_REF 38 VCCO_PECL
Top View
Jitter attenuation of a recovered communications clock CLK1 12 37 MP
VCC 13 36 NPB0
Complex-ratio clock frequency translation between
14
SEL1 35 NPB1
various communication protocols, such as:
SEL0 15 34 NPB2
For telecom, OC-12 to E3 rate conversion, 622.08MHz
CLK2 16 33 VCCA
to 34.368MHz, PLL ratio of 179/32
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
For digital video, ITU-R601 to SMPTE 252M/59.94,
27MHz to 74.17582MHz, PLL ratio of 250/91
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT / ICS VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 1 ICS843002BY-31 REV. C February 23, 2009
XOIN12
VCCA_XO
XOIN11
XTAL_IN
XOIN10
XTAL_OUT
XOIN9
XOFB0
XOIN8
XOFB1
XOIN7
XOFB2
XOIN6
XOFB3
XOIN5
XOFB4
XOIN4
XOFB5
XOIN3
XOFB6
XOIN2
XOFB7
XOIN1
XOFB8
XOIN0
XOFB9
NPA2 XOFB10
NPA1 XOFB11
NPA0
XOFB12ICS843002-31
FEMTOCLOCKS VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR PRELIMINARY
BLOCK DIAGRAM - NOMINAL SYSTEM CONFIGURATION
3
NPB[2:0]
3
NPA[2:0]
2
NV[1:0]
VCXO PLL Output
ISET
Divider NV[1:0]
Charge Pump Current VCLK
00: 1
External Loop
CLK0
01: 12
Filter Connection
00 10: 16
17.5 - 25MHz
nCLK0
LF0 LF1
11: Disabled Drive Low
QA Output
Divider NPA[2:0]
CLK1
01
000: 1
001: 2
FemtoClock
Input Divider
010: 4
Frequency
QA
011: 8
XOIN[12:0] VCXO PLL
nQA
Multiplier
CLK2 10
100: 12
1 to 8191
101: 14
0: x32 110: 16
QB Output
111: Disabled
1: x28
Divider NPB[2:0]
11 Bypass
Drive Low
VCXO PLL
000: QA 1
Feedback Divider
001: QA 2
010: QA 4
QB
SEL1 XOFB[12:0]
011: QA 8
nQB
1 to 8191
SEL0
100: XOIN Output
13 >1 1
101: OFB Output
XOIN[12:0]
110: MP Output
111: Disabled
13
XOFB[12:0]
Drive Low
MP
REF_CLK
OE_REF
LOCK
LOCK Detect
NOTE 1: For application configuration (non-test/bypass modes).
NOTE 2: Bold lines are primary clock paths (non-control/non-feedback lines).
Not all control lines and signal paths are shown in this simplified block diagram.
IDT / ICS VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 2 ICS843002BY-31 REV. C February 23, 2009
XTAL_OUT
XTAL_IN