Product Information

85356AGILF

85356AGILF electronic component of Renesas

Datasheet
Encoders, Decoders, Multiplexers & Demultiplexers 2:1 Diff-to-3.3V LVPECL/ECL Clk Mux

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - Global Stock

MOQ : 74
Multiples : 74

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85356AGILF
Renesas

74 : USD 13.5658
148 : USD 12.7823
296 : USD 11.9989
444 : USD 11.3461
740 : USD 11.085
N/A

Obsolete
0 - Global Stock

MOQ : 74
Multiples : 74

Stock Image

85356AGILF
Renesas

74 : USD 12.6882
148 : USD 12.096
296 : USD 11.5038
518 : USD 11.0628
1036 : USD 10.9116
2516 : USD 10.7352
N/A

Obsolete
     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
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Number of Input Lines
Number of Output Lines
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
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Number Of Lines In/Out
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Q1 2:1, Differential-to-3.3V Dual 85356 LVPECL/ECL Clock Multiplexer DATA SHEET General Description Features The 85356 is a dual 2:1 Differential-to-LVPECL Multiplexer. The High speed differential muliplexer. The device can be configured as a 2:1 multiplexer device has both common select and individual select inputs. When COM SEL is logic High, the CLKxx input pairs will be passed to the Dual 3.3V LVPECL outputs output. When COM SEL is logic Low, the output is determined by Selectable differential CLKx/nCLKx input pairs the setting of the SEL0 pin for channel 0 and the SEL1 pin for Differential CLKx/nCLKx pairs can accept the following interface Channel 1. levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL The differential input has a common mode range that can accept Output frequency: 900MHz (typical) most differential input types such as LVPECL, LVDS, LVHSTL, Translates any single-ended input signal to 3.3V LVPECL levels SSTL, and HCSL. The 85356 can therefore be used as a differential with resistor bias on nCLKx input translator to translate almost any differential input type to LVPECL. It Output skew: 75ps (typical) can also be used in ECL mode by setting V = 0V and V to -3.0V CC EE to - 3.8V. Propagation delay: 1.15ns (typical) LVPECL mode operating voltage supply range: The 85356 adds negligible jitter to the input clock and can operate at V = 3V to 3.8V, V = 0V high frequencies in excess of 900MHz thus making CC EE it ideal for use in demanding applications such as SONET, ECL mode operating voltage supply range: V = 0V, V = -3V to -3.8V Fibre Channel, 1 Gigabit/10 Gigabit Ethernet. CC EE -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown CLK0A CLK0A 1 20 VCC 0 Pullup nCLK0A 2 19 Q0 nCLK0A Q0 nc 3 18 nQ0 Pulldown CLK0B nQ0 CLK0B 4 17 SEL0 1 Pullup CLK0B nCLK0B 5 16 COM SEL CLK1A 6 15 SEL1 Pullup nCLK1A 7 14 VCC SEL0 nc 8 13 Pulldown COM SEL CLK1B 9 12 nQ1 nCLK1B 10 11 VEE Pullup SEL1 85356 Pulldown CLK1A 0 Pullup nCLK1A Q1 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body Pulldown CLK1B nQ1 1 Pullup M Package CLK1B Top View 85356 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View 85356 Rev C 1/5/15 1 2015 Integrated Device Technology, Inc.85356 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 14, 20 V Power Positive supply pins. CC 1 CLK0A Input Pulldown Non-inverting differential clock input. 2 nCLK0A Input Pullup Inverting differential clock input. 3, 8 nc Unused No connect. 4 CLK0B Input Pulldown Non-inverting differential clock input. 5 nCLK0B Input Pullup Inverting differential clock input. 6 CLK1A Input Pulldown Non-inverting differential clock input. 7 nCLK1A Input Pullup Inverting differential clock input. 9 CLK1B Input Pulldown Non-inverting differential clock input. 10 nCLK1B Input Pullup Inverting differential clock input. 11 V Power Negative supply pin. EE 12, 13 nQ1,Q1 Output Differential output pair. LVPECL interface levels. 15, 17 Input Pullup Clock select inputs. LVCMOS/LVTTL interface levels. SEL1, SEL0 16 Input Pulldown Common select input. LVCMOS/LVTTL interface levels. COM SEL 18, 19 nQ0,Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Function Tables Table 3. Control Input Function Table Inputs Outputs COM SEL SEL1 SEL0 Q0 nQ0 Q1 nQ1 0 0 0 CLK0A nCLK0A CLK1A nCLK1A 0 0 1 CLK0B nCLK0B CLK1A nCLK1A 0 1 0 CLK0A nCLK0A CLK1B nCLK1B 0 1 1 CLK0B nCLK0B CLK1B nCLK1B 1 x x CLK0B nCLK0B CLK1B nCLK1B Rev C 1/5/15 2 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL/ECL CLOCK MULTIPLEXER

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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