89HPES24T3G2 24-Lane 3-Port Datasheet Gen2 PCI Express Switch Dynamic link width reconfiguration for power/performance Device Overview optimization The 89HPES24T3G2 is a member of IDTs PRECISE family of PCI Configurable downstream port PCI-to-PCI bridge device Express switching solutions. The PES24T3G2 is a 24-lane, 3-port numbering Gen2 peripheral chip that performs PCI Express base switching with a Crosslink support feature set optimized for high performance applications such as servers, Supports ARI forwarding defined in the Alternative Routing-ID storage, and communications systems. It provides connectivity and Interpretation (ARI) ECN for virtualized and non-virtualized switching functions between a PCI Express upstream port and two environments downstream ports and supports switching between downstream ports. Ability to load device configuration from serial EEPROM u Legacy Support Features u PCI compatible INTx emulation High Performance PCI Express Switch Supports bus locked transactions, allowing use of PCI Express Twenty-four 5 Gbps Gen2 PCI Express lanes supporting with legacy software 5 Gbps and 2.5 Gbps operation u Highly Integrated Solution Up to three switch ports Support for Max Payload Size up to 2048 bytes Requires no external components Supports one virtual channel and eight traffic classes Incorporates on-chip internal memory for packet buffering and queueing Fully compliant with PCI Express base specification Revision 2.0 Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes, u 8B/10B encoder/decoder (no separate transceivers needed) Flexible Architecture with Numerous Configuration Options u Reliability, Availability, and Serviceability (RAS) Features Automatic per port link width negotiation to x8, x4, x2, or x1 Ability to disable peer-to-peer communications Automatic lane reversal on all ports Supports ECRC and Advanced Error Reporting Automatic polarity inversion All internal data and control RAMs are SECDED ECC Supports in-band hot-plug presence detect capability protected Supports external signal for hot plug event notification allowing Supports PCI Express hot-plug on all downstream ports SCI/SMI generation for legacy operating systems Supports upstream port hot-plug Block Diagram 3-Port Switch Core / 24 Gen2 PCI Express Lanes Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Phy Phy Phy Phy Phy Phy Phy Phy Phy Logical Logical Logical Logical Logical Logical Logical Logical Logical Layer Layer Layer Layer Layer Layer Layer Layer Layer ..... SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 50 December 16, 2013 DSC 6930IDT 89HPES24T3G2 Datasheet Hot-swap capable I/O Revision 2.0. The PES24T3G2 can operate either as a store and External Serial EEPROM contents are checksum protected forward or cut-through switch and is designed to switch memory and I/O Supports PCI Express Device Serial Number Capability transactions. It supports eight Traffic Classes (TCs) and one Virtual Capability to monitor link reliability and autonomously change Channel (VC) with sophisticated resource management to enable effi- link speed to prevent link instability cient switching and I/O connectivity for servers, storage, and embedded u Power Management processors with limited connectivity. Utilizes advanced low-power design techniques to achieve low typical power consumption Support PCI Power Management Interface specification (PCI- Processor Processor PM 1.1) Supports device power management states: D0, D3 and hot D3 cold Memory Support for PCI Express Active State Power Management North Memory Memory Memory Bridge (ASPM) link state Supports link power management states: L0, L0s, L1, L2/L3 x8 Ready and L3 Supports PCI Express Power Budgeting Capability PES24T3G2 Configurable SerDes power consumption Supports optional PCI-Express SerDes Transmit Low-Swing x8 x8 Voltage Mode Supports numerous SerDes Transmit Voltage Margin I/O Dual I/O I/O settings PCI Express 10GbE SATA SATA Slot Unused SerDes are disabled u Testability and Debug Features Figure 2 I/O Expansion Application Per port link up and activity status outputs available on I/O expander outputs SMBus Interface Built in SerDes 8-bit and 10-bit pseudo-random bit stream (PRBS) generators The PES24T3G2 contains two SMBus interfaces. The slave inter- Numerous SerDes test modes, including a PRBS Master face provides full access to the configuration registers in the Loopback mode for in-system link testing PES24T3G2, allowing every configuration register in the device to be Ability to read and write any internal register via SMBus and read or written by an external agent. The master interface allows the JTAG interfaces, including SerDes internal controls default configuration register values of the PES24T3G2 to be over- Per port statistics and performance counters, as well as propri- ridden following a reset with values programmed in an external serial etary link status registers EEPROM. The master interface is also used by an external Hot-Plug I/O u General Purpose Input/Output Pins expander. Each pin may be individually configured as an input or output Six pins make up each of the two SMBus interfaces. These pins Each pin may be individually configured as an interrupt input consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus Some pins have selectable alternate functions address pins. In the slave interface, these address pins allow the u Option A Package: 19mm x 19mm 324-ball Flip Chip BGA SMBus address to which the device responds to be configured. In the with 1mm ball spacing master interface, these address pins allow the SMBus address of the u Option B Package: 27mm x 27mm 676-ball Flip Chip BGA serial configuration EEPROM from which data is loaded to be config- with 1mm ball spacing ured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, Product Description the resulting address is assigned as shown in Table 1. Utilizing standard PCI Express interconnect, the PES24T3G2 Note: MSMBADDR and SSMBADDR address pins are not provides the most efficient I/O connectivity solution for applications available in the 19mm package. The MSMBADDR address is requiring high throughput, low latency, and simple board layout with a hardwired to 0x50, and the SSMBADDR address is hardwired minimum number of board layers. It provides connectivity for up to 3 to 0x77. ports across 24 integrated serial lanes. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5 Gbps, and mixed 5 Gbps / 2.5Gbps modes. The PES24T3G2 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification 2 of 50 December 16, 2013