8A34004 Datasheet Synchronization Management Unit 4 Differential / 8 LVCMOS outputs Overview Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS) The 8A34004 Synchronization Management Unit (SMU) provides Jitter below 150fs RMS (10kHz to 20MHz) tools to manage timing references, clock sources, and timing LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL paths for IEEE 1588 and Synchronous Ethernet (SyncE) based output modes supported clocks. The PLL channels can act independently as frequency Differential output swing is selectable: 400mV / 650mV / synthesizers, jitter attenuators, Digitally Controlled Oscillators 800mV / 910mV (DCO), or Digital Phase Lock Loops (DPLL). Independent output voltages of 3.3V, 2.5V, or 1.8V Optional clock recovery filter/servo software is available under LVCMOS additionally supports 1.5V or 1.2V license from Renesas for use with the 8A34004. The filter/servo The clock phase of each output is individually programmable software is designed to suppress the affects of Packet Delay in 1ns to 2ns steps with a total range of 180 Variation (PDV) on packet based timing signals it can be used 2 differential / 4 single-ended clock inputs with protocol stacks for IEEE 1588 or other packet-based timing Support frequencies from 0.5Hz to 1GHz protocols. Any input can be mapped to any or all of the timing channels Redundant inputs frequency independent of each other Typical Applications Any input can be designated as external frame/sync pulse of Core and access IP switches / routers EPPS (even pulse per second), 1 PPS (Pulse per Second), Synchronous Ethernet equipment 5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz associated with a selectable reference clock input Telecom Boundary Clocks (T-BCs) and Telecom Time Slave Clocks (T-TSCs) according to ITU-T G.8273.2 Per-input programmable phase offset of up to 1.638 s in 1ps steps 10Gb, 40Gb, and 100Gb Ethernet interfaces Reference monitors qualify/disqualify references depending on Central Office Timing Source and Distribution LOS, activity, frequency monitoring, and/or LOS input pins Wireless infrastructure for 4.5G and 5G network equipment Loss of Signal (LOS) input pins (via GPIOs) can be assigned to any input clock reference Features Automatic reference selection state machines select the active Two independent timing channels reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive, and other Each can act as a frequency synthesizer, jitter attenuator, programmable settings Digitally Controlled Oscillator (DCO), or Digital Phase Lock Loop (DPLL) System APLL operates from fundamental-mode crystal: 25MHz to 54MHz or from a crystal oscillator DPLLs generate telecom compliant clocks System DPLL accepts an XO, TCXO, or OCXO operating at Compliant with ITU-T G.8262 for Synchronous Ethernet virtually any frequency from 1MHz to 150MHz Compliant with legacy SONET/SDH and PDH DPLLs can be configured as DCOs to synthesize Precision requirements Time Protocol (PTP) / IEEE 1588 clocks DPLL Digital Loop Filters (DLFs) are programmable with cut DCOs generate PTP based clocks with frequency resolution off frequencies from 12Hz to 22kHz -16 less than 1.11 10 DPLL/DCO channels share frequency information using the DPLL Phase detectors can be used as Time-to-Digital Combo Bus to simplify compliance with ITU-T G.8273.2 Converters (TDC) with precision below 1ps Switching between DPLL and DCO modes is hitless and 2 Supports 1MHz I C or 50MHz SPI serial processor ports dynamic The device can configure itself automatically after reset via: Automatic reference switching between DCO and DPLL Internal customer definable One-Time Programmable modes to simplify support for an external phase/time input memory with up to 16 different configurations interface in a T-BC 2 2 Standard external I C EPROM via separate I C Master Port Generates output frequencies that are independent of input 1149.1 JTAG Boundary Scan frequencies via a Fractional Output Divider (FOD) 7 7 mm 48-VFQFPN package Each FOD supports output phase tuning with 1ps resolution 2020 Renesas Electronics Corporation 1 September 28, 20208A34004 Datasheet Block Diagram Figure 1. Block Diagram OSCI OSCO XO DPLL To FODs System Osc FOD DPLL System Combo Bus APLL (Frequency Data) Div Q8 Reference Monitors DPLL / FOD Div Q9 DCO 5 Reference Switching DPLL / FOD Div Q10 CLK0 State DCO 6 Machines Div Q11 CLK1 PWM DPLL / Decoders FOD DCO 2 TOD Status and Configuration OTP Registers PWM 2 2 I C Master SPI/I C GPIO / JTAG Encoders Description The 8A34004 is a Synchronization Management Unit (SMU) for packet based and physical layer based equipment synchronization. The 8A34004 is a highly integrated device that provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO) or Digital Phase Lock Loops (DPLL). The 8A34004 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces, as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs). The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal connected between the OSCI and OSCO pins. The System DPLL generates an internal system clock that is used by the reference monitors and other digital circuitry in the device. If the reference provided to the System APLL meets the stability and accuracy requirements of the intended application then the System DPLL can free run and a System DPLL reference is not required. Alternatively the System DPLL can be locked to an external reference that meets the stability and accuracy requirements of the intended application. The System DPLL can accept a reference from the XO DPLL pin or via the reference selection mux. 2020 Renesas Electronics Corporation 2 September 28, 2020