Differential-to-LVPECL/ECL Fanout Buffer ICS8S58021I DATA SHEET General Description Features The ICS8S58021I is a high speed 1-to-4 Differential- Four LVPECL/ECL outputs ICS to-LVPECL/ECL Fanout Buffer. The ICS8S58021I is IN, nIN input can accept the following differential input levels: HiPerClockS optimized for high speed and very low output skew, LVPECL, LVDS, CML making it suitable for use in demanding applications 50 internal input termination to V T such as SONET, 1 Gigabit and 10 Gigabit Ethernet, Output frequency: 2.5GHz (maximum) and Fibre Channel. The internally terminated differential input and Output skew: 30ps (maximum) VREF AC pin allow other differential signal families such as LVDS, LVPECL and CML to be easily interfaced to the input with minimal Part-to-part skew: 150ps (maximum) use of external components. The ICS8S58021I is packaged in a Additive phase jitter, RMS: 0.02ps (typical) small 3mm x 3mm 16-pin VFQFN package which makes it ideal for Propagation Delay: 425ps (maximum) use in space-constrained applications. LVPECL mode operating voltage supply range: V = 2.375V to 3.465V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.465V to 2.375V CC EE -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Q0 16 15 14 13 nQ0 IN 1 12 Q1 IN nQ1 VT 2 11 V T Q1 V 3 10 Q2 REF-AC nIN 4 9 nQ2 nQ1 nIN 56 7 8 V REF AC Q2 ICS8S58021I nQ2 16-Lead VFQFN 3mm x 3mm x 0.925mm package body Q3 K Package nQ3 Top View ICS8S58021AKI REVISION A FEBRUARY 22, 2010 1 2010 Integrated Device Technology, Inc. V EE VEE nQ3 Q0 Q3 nQ0 V V CC CCICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description Non-inverting LVPECL differential clock input. 1 IN Input R = 50 termination to V . T T Input for termination. Both IN, nIN inputs are terminated to this pin. See Application Information 2V Input T Termination Interface. section, Differential Input with Built-In 50 Output Reference voltage for AC-coupled applications. 3V REF AC termination to V . 4 nIN Input Inverting differential LVPECL clock input. RT = 50 T Power Negative supply pins. 5, 16 V EE 6, 7 nQ3, Q3 Output Differential output pair. LVPECL/ECL interface levels. 8, 13 V Power Power supply pins. cc 9, 10 nQ2, Q2 Output Differential output pair. LVPECL/ECL interface levels. 11, 12 nQ1, Q1 Output Differential output pair. LVPECL/ECL interface levels. 14, 15 nQ0, Q0 Output Differential output pair. LVPECL/ECL interface levels. ICS8S58021AKI REVISION A FEBRUARY 22, 2010 2 2010 Integrated Device Technology, Inc.