1:2 Differential-to-LVPECL 8S89874 Buffer/Divider Data Sheet General Description Features The 8S89874 is a high speed 1:2 Differential-to- LVPECL Buffer/ Two LVPECL/ECL output pairs Divider. The 8S89874 has a selectable 1, 2, 4, 8, 16 output Frequency divide select options: 1 (pass through), 2, 4, 8, divider, which allows the device to be used as either a 1:2 fanout 16 buffer or frequency divider. The clock input has internal termination IN, nIN input can accept the following differential input levels: resistors, allowing it to interface with several differential signal types LVPECL, LVDS, CML while minimizing the number of required external components. The Output frequency: 2GHz (maximum) device is packaged in a small, 3mm x 3mm VFQFN package, making Output skew: 15ps (maximum) it ideal for use on space-constrained boards. Part-to-part skew: 250ps (maximum) Additive phase jitter, RMS: 0.20ps (typical) LVPECL supply voltage range: 2.375V to 3.63V ECL supply voltage range: -3.63V to -2.375V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup S2 16 15 14 13 Pullup nRESET 1 12 IN Q0 Enable FF Q0 2 11 V nQ0 T Enable 0 MUX 8S89874 nQ0 10 3 V REF AC Q1 8XXXXXX 1 Q1 IN 00 2 50 9 4 nIN nQ1 nQ1 01 4 V T 5 6 78 10 8 50 11 16 nIN Pullup S0 Decoder Pullup S1 16-pin,3mmx3mmVFQFNPackage V REF AC 2016 Integrated Device Technology, Inc 1 Revision B February 9, 2016 S2 S0 nc S1 V CC V CC nRESET V EE8S89874 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL/ECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL/ECL interface levels. 5, 15, 16 S2, S1, S0 Input Pullup Select pins. LVCMOS/LVTTL interface levels. 6 nc Unused No connect. 7, 14 V Power Positive supply pins. cc When LOW, resets the divider. Pulled HIGH when left unconnected. Input threshold 8 nRESET Input Pullup is V /2. Includes a 37k pullup resistor. LVTTL/LVCMOS interface levels. CC 9 nIN Input Inverting differential LVPECL clock input. R = 50 termination to V . T T 10 V Output Reference voltage for AC-coupled applications. REF AC 11 V Input Termination input. T 12 IN Input Non-inverting LVPECL differential clock input. R = 50 termination to V . T T 13 V Power Negative supply pin. EE NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pullup Resistor 37 k PULLUP 2016 Integrated Device Technology, Inc 2 Revision B February 9, 2016