9DMU0131AKILF Renesas

2:1 1.5V PCIe Gen1-2-3 Clock Mux 9D M U 013 1 D A T A S H E E T General Description Features/Benefits The 9DMU0131 is a member of IDT s SOC-Friendly 1.5V LP-HCSL output saves 2 resistors compared to standard Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. The output HCSL output has an OE pin for optimal system control and power 1.5V operation 11mW typical power consumption management. The part provides asynchronous or glitch-free Selectable asynchronous or glitch-free switching allows switching modes. the mux to be selected at power up even if both inputs are not running, then transition to glitch-free switching mode Recommended Application Spread Spectrum Compatible supports EMI reduction OE pin supports DIF power management 2:1 1.5V PCIe Gen1-2-3 Clock Mux HCSL differential inputs can be driven by common clock sources Output Features 1MHz to 167MHz operating frequency 1 Low-Power (LP) HCSL DIF pair Space saving 16-pin 3x3mm VFQFPN minimal board space Key Specifications DIF add iti ve cycle-to-cycle jitter <5ps DIF phase jitter is PCIe Gen1-2-3 compliant 125MHz additive phase jitter 535fs rms typical (12kHz to 20MHz) Block Diagram OE0 DIF INA A DIF0 DIF INB B vSW MODE SEL A B 9DMU0131 REVISION A 09/30/14 19DMU0131 DATASHEET Pin Configuration Power Management Table Power Connections DIFx OEx Pin DIF IN True O/P Comp. O/P 0 Running Running Running 1 Running Low Low Note: Pins 2 and 3 should be decoupled separately to pins 1 and 4 respectively. Pin Descriptions 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX 2 REVISION A 09/30/14