6-Output Very Low-Power PCIe Gen 1-2-3-4 9FGV0641 Clock Generator with Zo=100ohms DATASHEET Description Features The 9FGV0641 is a member of IDT s SOC-Friendly 1.8V very LP-HCSL outputs with integrated terminations save 24 low-power PCIe clock family. The device has integrated 100 resistors compared to standard PCIe devices output terminations providing direction connection to 100 54mW typical power consumption reduced thermal transmission lines. The device also has 6 output enables for concerns clock management and supports 2 different spread spectrum Outputs can optionally be supplied from any voltage levels in addition to spread off. between 1.05V and 1.8V maximum power savings OE pins support DIF power management Typical Applications Programmable slew rate for each output allows tuning for various line lengths PCIe Gen14 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Programmable output amplitude allows tuning for various application environments DIF outputs blocked until PLL is locked clean system Output Features start-up 6 100MHz Low-Power (LP) HCSL DIF pairs with Zo = Selectable 0%, -0.25% or -0.5% spread on DIF outputs 100 reduces EMI 1 1.8V LVCMOS REF output with Wake-On-LAN (WOL) External 25MHz crystal supports tight ppm with 0 ppm support synthesis error Configuration can be accomplished with strapping pins Key Specifications SMBus interface not required for device control DIF cycle-to-cycle jitter <50ps 3.3V tolerant SMBus interface works with legacy controllers DIF output-to-output skew <50ps Selectable SMBus addresses multiple devices can easily share an SMBus segment DIF phase jitter is PCIe Gen1-2-3-4 compliant Space saving 5 x 5 mm 40-VFQFPN minimal board space REF phase jitter is < 1.5ps RMS Block Diagram vOE(5:0) 6 REF1.8 XIN/CLKIN 25 OSC X2 DIF5 DIF4 SS Capable PLL DIF3 vSADR DIF2 vSS EN tri DIF1 CKPWRGD PD CONTROL LOGIC SDATA 3.3 DIF0 SCLK 3.3 9FGV0641 JUNE 6, 2019 19FGV0641 DATASHEET Pin Configuration 40 39 38 37 36 35 34 33 32 31 vSS EN tri130 vOE3 X1 25229 DIF3 X2 DIF3 328 VDDXTAL1.8427 VDDIO 9FGV0641A VDDREF1.8526 VDDA1.8 vSADR/REF1.8625 NC Paddle is GND NC724 vOE2 GNDDIG DIF2 823 SCLK 3.3922 DIF2 SDATA 3.3 10 21 vOE1 11 12 13 14 15 16 17 18 19 20 40-VFQFPN, 5 x 5 mm, 0.4mm pitch v prefix indicates internal 120kOhm pull-down resistor prefix indicates internal 120kOhm pull-up resistor SMBus Address Selection Table + Read/Write Bit SADR Address State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 x Power Management Table SMBus DIFx REF CKPWRGD PD OE bit OEx True O/P Comp. O/P 1 0 X X Low Low Hi-Z 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD VDDIO GND 441XTAL OSC 5 41 REF Power Digital (dirty) 11 8 Power 12,17,27,32,39 41 DIF outputs 26 41 PLL Analog 6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR WITH ZO=100OHMS 2 JUNE 6, 2019 VDDDIG1.8 CKPWRGD PD VDDIO VDDIO vOE0 vOE5 DIF0 DIF5 DIF0 DIF5 VDD1.8 vOE4 VDDIO DIF4 DIF1 DIF4 DIF1 VDDIO NC VDD1.8