9ZML1256AKILFT

9ZML1245/9ZML1255/ 9ZML1256 2:12 Clock Multiplexer for PCIe Gen15 and UPI Datasheet Description Features 12 Low-power HCSL (LP-HCSL) outputs The 9ZML1245/9ZML1255/9ZML1256 devices are third generation enhanced performance 2-input, 12-output clock Integrated terminations for 85 (9ZXL1255/56) and 100 multiplexers. Each input clock has software adjustable (9ZXL1245) systems eliminate up to 4 resistors per output pair input-to-output delay when operating in Zero-Delay (ZDB) mode. Flexible Power Sequencing (FPS) configuration via SMBus The devices also implement an extensive set of features ensuring Power Down Tolerant input (PDT) inputs: SEL A B , that clocks are well behaved with today s ever more complex SADR 1:0 tri, OE pins power-up sequencing. The 9ZML1256 has an SMBus Write Input-to-output delay: 0ps default. Programmable through 360 Lockout pin for increased device and system security. 2 software-configurable input-to-output delay lines PCIe Clocking Architectures Dedicated OE pins support PCIe CLKREQ function Common Clocked (CC) Up to 9 selectable SMBus addresses (9ZXL1245/55) Independent Reference (IR) with and without spread spectrum SMBus Write Protect Pin (9ZXL1256) Selectable ZDB bandwidths minimizes jitter peaking in Key Specifications cascaded ZDB topologies Hardware/SMBus control of ZDB and FOB modes Fanout Buffer Mode additive phase jitter: PCIe Gen5 CC < 15fs RMS Spread-spectrum compatible Up to 400MHz FOB operation DB2000Q additive jitter < 25fs RMS 100MHz ZDB mode operation QPI/UPI 11.4GB/s < 40fs RMS -40C to +85C operating temperature range IF-UPI additive jitter < 70fs RMS ZDB Mode phase jitter: 10 10 mm 72-VFQFPN package PCIe Gen5 CC < 24fs RMS Typical Applications QPI/UPI 11.4GB/s < 110fs RMS Servers/High-performance Computing IF-UPI additive jitter < 130fs RMS nVME Storage Cycle-to-cycle jitter < 50ps Networking Output-to-output skew < 50ps Accelerators Industrial Control Block Diagram VDDR VDDA VDD x3 VDDIO x4 FBOUT NC FBOUT NC PLL DIF INA DIF11 DIF INA DIF11 DIF INA DIF INA SEL A B 12 outputs HIBW BYPM-LOBW Control Logic CKPWRGD PD 9ZML1256 OE 11:0 only vSMB WRTLOCK DIF0 vSADR1 tri SMBus Factory DIF0 vSADR0 tri 9ZML1245/55 Engine Configuration SMBCLK only SMBDAT Resistors are integrated GNDA GND x7 2021 Renesas Electronics Corporation 1 R31DS0023EU0600 May 12, 20219ZML1245/9ZML1255/9ZML1256 Datasheet Contents Description 1 PCIe Clocking Architectures . 1 Key Specifications 1 Features 1 Typical Applications . 1 Block Diagram . 1 Pin Assignments 3 9ZML1245/9ZML1255 . 3 9ZML1256 4 Pin Descriptions 5 Absolute Maximum Ratings . 8 Thermal Characteristics 9 Electrical Characteristics . 9 Power Management 17 Skew Programming 17 Test Loads . 18 Alternate Terminations 19 General SMBus Serial Interface Information . 20 How to Write . 20 How to Read . 20 Package Outline Drawings . 25 Marking Diagram 25 Ordering Information . 25 Revision History . 26 2021 Renesas Electronics Corporation 2 R31DS0023EU0600 May 12, 2021