9ZXL1530DKILF Renesas

9ZXL15x0D/9ZXL19x0D/ 15 to 19-Output Buffers for 9ZXL1951D PCIe Gen15 and UPI Datasheet Description Features LP-HCSL outputs eliminate up to 4 resistors per output pair The 9ZXL15x0D/9ZXL19x0D/9ZXL1951D devices comprise a family of 2nd-generation enhanced performance buffers for PCIe 9 selectable SMBus addresses and CPU applications. The family meets all published QPI/UPI, Selectable PLL bandwidths minimizes jitter peaking in DB2000Q and PCIe Gen15 jitter specifications. Devices are cascaded PLL topologies either 15 or 19 outputs. The devices function as both fanout (FOB) Hardware/SMBus control of ZDB and FOB modes allow and zero-delay (ZDB) buffers. All devices meet DB2000Q and change without power cycle DB1900Z jitter and skew requirements. 8 OE pins support PCIe CLKREQ functionality (9ZXL1951) Key Specifications Spread spectrum compatible 100MHz and 133.33MHz ZDB mode (9ZXL15x0, 9ZXL19x0) ZDB Mode phase jitter: 100MHz ZDB mode (9ZXL1951) PCIe Gen5 CC < 22fs RMS (Low Bandwidth) 1400MHz FOB mode (all devices) QPI/UPI 11.4GB/s < 120fs RMS (Low Bandwidth) -40C to +85C operating temperature range IF-UPI additive jitter < 130fs RMS (Low Bandwidth) Package information: see Ordering Information table Fanout Buffer Mode additive phase jitter: PCIe Gen5 CC < 24fs RMS PCIe Clocking Architectures DB2000Q additive jitter < 39fs RMS Common Clocked (CC) QPI/UPI 11.4GB/s < 40fs RMS Independent Reference (IR) with and without spread spectrum IF-UPI additive jitter < 70fs RMS Cycle-to-cycle jitter: < 50ps Typical Applications Output-to-output skew: < 50ps Servers nVME Storage Outputs Networking 15 or 19 Low-power HCSL (LP-HCSL) output pairs Accelerators Industrial Block Diagram 9ZXL15x0, 9ZXL19x0 only VDDIO VDDR VDDA VDDO 9ZXL1951 only FBOUT NC FBOUT NC PLL DIF IN DIFn DIF IN DIFn 9ZXL15x0, 9ZXL19x0 only 100M 133M 15 or 19 SADR 1:0 tri SMBus Factory outputs 9ZXL1951 has Engine Configuration SMBCLK pull-down on SMBDAT these pins DIF0 v HIBW BYPM-LOBW 9ZXL1951 does DIF0 CKPWRGD PD Control Logic not have pull-up OE 5:12 on this pin 9ZXL1951 only 9ZXL15x0, 9ZXL19x0 only GNDA EPAD/GND Pins with prefix have internal 120kohm pull-up Pins with v prefix have internal 120kohm pull-down Pins with v prefix have internal 120kohm pull-up/pull-down (biased to VDD/2) 2020 Renesas Electronics Corporation 1 August 25, 20209ZXL15x0D/9ZXL19x0D/9ZXL1951D Datasheet Contents Description 1 Key Specifications 1 Outputs . 1 Features 1 PCIe Clocking Architectures . 1 Typical Applications . 1 Block Diagram . 1 Pin Assignments 3 9ZXL15x0D Pin Assignment 3 9ZXL19x0D Pin Assignment 4 9ZXL1951D Pin Assignment 5 Pin Descriptions 6 Absolute Maximum Ratings 11 Thermal Characteristics . 11 Electrical Characteristics 12 Test Loads . 21 Package Outline Drawings . 28 Marking Diagrams . 28 9ZXL15x0D 28 9ZXL19x0D 29 9ZXL1951D 29 Ordering Information . 30 Revision History . 31 2020 Renesas Electronics Corporation 2 August 25, 2020