TM HS-3282 REFERENCE AN400 CMOS ARINC Bus Interface Circuit March 1997 Features Description ARlNC Specification 429 Compatible The HS-3282 is a high performance CMOS bus interface circuit that is intended to meet the requirements of ARINC Data Rates of 100 Kilobits or 12.5 Kilobits Specification 429, and similar encoded, time multiplexed Separate Receiver and Transmitter Section serial data protocols. This device is intended to be used with the HS-3182, a monolithic Dl bipolar differential line driver Dual and Independent Receivers, Connecting Directly designed to meet the specifications of ARINC 429. The to ARINC Bus ARINC 429 bus interface circuit consists of two (2) receivers and a transmitter operating independently as shown in Serial to Parallel Receiver Data Conversion Figure 1. The two receivers operate at a frequency that is Parallel to Serial Transmitter Data Conversion ten (10) times the receiver data rate, which can be the same or different from the transmitter data rate. Although the two Word Lengths of 25 or 32 Bits receivers operate at the same frequency, they are Parity Status of Received Data functionally independent and each receives serial data asyn- chronously. The transmitter section of the ARINC bus Generate Parity of Transmitter Data interface circuit consists mainly of a First-In First-Out (FIFO) Automatic Word Gap Timer memory and timing circuit. The FIFO memory is used to hold up to eight (8) ARINC data words for transmission serially. Single 5V Supply The timing circuit is used to correctly separate each ARINC Low Power Dissipation word as required by ARINC Specification 429. Even though ARINC Specification 429 specifies a 32-bit word, including Full Military Temperature Range parity, the HS-3282 can be programmed to also operate with a word length of 25 bits. The incoming receiver data word Ordering Information parity is checked, and a parity status is stored in the receiver latch and output on Pin BD08 during the 1st word. A logic PKG. PACKAGE TEMP. RANGE PART NUMBER NO. 0 indicates that an odd number of logic 1 s were received o o and stored a logic 1 indicates that an even number of logic CERDIP -55 C to +125 C HS1-3282-8 F40.6 1s were received and stored . In the transmitter the parity SMD 5962-8688001QA F40.6 generator will generate either odd or even parity depending o o CLCC -40 C to +85 C HS4-3282-9+ J44.A upon the status of PARCK control signal. A logic 0 on o o BD12 will cause odd parity to be used in the output data -55 C to +125 C HS4-3282-8 J44.A stream. SMD 5962-8688001XA J44.A Versatility is provided in both the transmitter and receiver by the external clock input which allows the bus interface circuit to operate at data rates from 0 to 100 kilobits. The external clock must be ten (10) times the data rate to insure no data ambiguity. The ARINC bus interface circuit is fully guaranteed to support the data rates of ARINC specification 429 over both the voltage ( 5%) and full military temperature range. It interfaces with UL, CMOS or NMOS support circuitry, and uses the standard 5-volt V supply. CC CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. FN2964.2 1-888-INTERSIL or 321-724-7143 Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. All Rights Reserved 183HS-3282 Pinouts HS-3282 (CERDIP) TOP VIEW V 1 40 NC DD 429DI1(A) 2 39 MR 429DI1(B) 3 38 TX CLK 429DI2(A) 4 37 CLK 429DI2(B) 5 36 NC D/R1 6 35 NC D/R2 7 34 CWSTR SEL 8 33 ENTX EN1 9 429D0 32 EN2 10 31 429D0 BD15 11 30 TX/R BD14 12 29 PL2 BD13 13 28 PL1 BD12 14 27 BD00 BD11 15 26 BD01 16 BD02 BD10 25 BD09 17 24 BD03 BD08 18 23 BD04 BD07 19 22 BD05 BD06 20 21 GND HS-3282 (CLCC) TOP VIEW 6 5 4 3 2 44 43 42 41 40 1 NC 7 39 NC D/R1 8 38 NC 9 D/R2 37 CWSTR 10 SEL 36 ENTX EN1 11 429D0 35 12 429D0 EN2 34 BD15 13 TX/R 33 BD14 14 32 PL2 15 PL1 BD13 31 BD12 16 BD00 30 BD11 17 29 BD01 18 19 20 21 22 23 24 25 26 27 28 184 NC NC 429DI2(B) BD10 BD09 429DI2(A) 429DI1(B) BD08 429DI1(A) BD07 V BD06 DD GND NC BD05 MR BD04 TXCLK BD03 CLK BD02 NC