ISL6115AEVAL1Z Renesas

DATASHEET ISL6115A FN6855 Rev 1.00 12V Power Distribution Controllers April 23, 2010 This fully featured hot swap power controller targets Features +12V applications. The ISL6115A with its integrated HOT SWAP Single Power Distribution Control for charge pump has a higher (6.5V vs 5V) gate drive +12V than its sister part the ISL6115 making this part an Overcurrent Fault Isolation immediate efficiency improvement replacement. Programmable Current Regulation Level This IC features programmable overcurrent (OC) Programmable Current Regulation Time to detection, current regulation (CR) with time delay to Latch-Off latch-off and soft-start. Rail-to-Rail Common Mode Input Voltage Range The current regulation level is set by 2 external Enhanced Internal Charge Pump Drives N-Channel resistors R sets the CR Vth and the other is a ISET MOSFET gate to 6.5V above IC bias. low ohmic sense resistor across, which the CR Vth is developed. The CR duration is set by an external Undervoltage and Overcurrent Latch Indicators capacitor on the CTIM pin, which is charged with a Adjustable Turn-On Ramp 20A current once the CR Vth level is reached. The Protection During Turn-On IC then quickly pulls down the GATE output latching Two Levels of Overcurrent Detection Provide Fast off the pass FET. Response to Varying Fault Conditions 1s Response Time to Dead Short Pb-Free (RoHS Compliant) Applications Power Distribution Control Hot Plug Components and Circuitry Application Circuits - High Side Controller LOAD + - 1 8 PWRON ISL6115A 2 7 PGOOD 3 6 OC 4 5 +12V +V SUPPLY TO BE CONTROLLED FN6855 Rev 1.00 Page 1 of 10 April 23, 2010ISL6115A Simplified Block Diagram V DD + - POR + R QN 8V R I PWRON SET - Q S UV - + + V REF - ENABLE 12V I SEN PGOOD 20A UV DISABLE CLIM OC + - 7.5k CTIM GATE + FALLING - - EDGE + 10A + DELAY 1.86V WOCLIM - 18V ENABLE 20A V RISING V SS DD 18V EDGE PULSE Pin Configuration ISL6115A (8 LD SOIC) TOP VIEW ISET 1 8 PWRON ISEN 2 7 PGOOD GATE 3 6 CTIM VSS 4 5 VDD Ordering Information PART NUMBER PART TEMPERATURE PACKAGE PKG. (Notes 2, 3) MARKING RANGE (C) (Pb-free) DWG. ISL6115AIBZ 6115A IBZ -40 to +85 8 Ld SOIC M8.15 ISL6115AIBZ-T (Notes 1, ) 6115A IBZ -40 to +85 8 Ld SOIC M8.15 ISL6115ACBZ 6115A CBZ 0 to +70 8 Ld SOIC M8.15 ISL6115ACBZ-T (Notes 1, ) 6115A CBZ 0 to +70 8 Ld SOIC M8.15 ISL6115AEVAL1Z Evaluation Platform NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6115A. For more information on MSL please see techbrief TB363. FN6855 Rev 1.00 Page 2 of 10 April 23, 2010