DATASHEET ISL6537 FN9142 Rev 6.00 ACPI Regulator/Controller for Dual Channel DDR Memory Systems Jul 18, 2007 The ISL6537 provides a complete ACPI compliant power Features solution for up to 4 DIMM dual channel DDR/DDR2 Memory Generates 4 Regulated Voltages systems. Included are both a synchronous buck controller to - Synchronous Buck PWM Controller for DDR V DDQ supply V during S0/S1 and S3 states. During S0/S1 DDQ - 3A Integrated Sink/Source Linear Regulator with state, a fully integrated sink-source regulator generates an Accurate VDDQ/2 Divider Reference for DDR V TT accurate (V /2) high current V voltage without the DDQ TT - LDO Regulator for GMCH Core need for a negative supply. A buffered version of the V /2 DDQ - LDO Regulator for CPU/GMCH V Termination reference is provided as V . Two LDO controllers are also TT REF integrated for the GMCH core voltage regulation and for the ACPI Compliant Sleep State Control GMCH and CPU V termination voltage regulation. TT Glitch-free Transitions During State Changes The switching PWM controller drives two N-Channel Integrated V Buffer REF MOSFETs in a synchronous-rectified buck converter PWM Controller Drives Low Cost N-Channel MOSFETs topology. The synchronous buck converter uses voltage- mode control with fast transient response. The switching 250kHz Constant Frequency Operation regulator provides a maximum static regulation tolerance of Tight Output Voltage Regulation 2% over line, load, and temperature ranges. The output is - All Outputs: 2% Over Temperature user-adjustable by means of external resistors down to 0.8V. Fully-Adjustable Outputs with Wide Voltage Range: Down An integrated soft-start feature brings all outputs into to 0.8V supports DDR and DDR2 Specifications regulation in a controlled manner when returning to S0/S1 Simple Single-Loop Voltage-Mode PWM Control Design state from any sleep state. During S0 the VIDPGD signal Fast PWM Converter Transient Response indicates that the GMCH and CPU V termination voltage TT is within spec and operational. Under and Overvoltage Monitoring on All Outputs Each output is monitored for undervoltage events. The OCP on the Switching Regulator switching regulator also has overvoltage and overcurrent Integrated Thermal Shutdown Protection protection. Thermal shutdown is integrated. Pb-Free Plus Anneal Available (RoHS Compliant) Pinout ISL6537 (6x6 QFN) Applications TOP VIEW Single and Dual Channel DDR Memory Power Systems in ACPI Compliant PCs Graphics Cards - GPU and Memory Supplies 28 27 26 25 24 23 22 ASIC Power Supplies 5VSBY 1 21 DRIVE4 Embedded Processor and I/O Supplies S3 2 20 REFADJ4 DSP Supplies 3 19 P12V DRIVE3 Ordering Information GND GND 4 18 FB3 29 PART PART TEMP. PKG. 5 17 DDR VTT FB4 NUMBER MARKING RANGE (C) PACKAGE DWG. DDR VTT 6 16 COMP ISL6537CR ISL6537CR 0 to +70 28 Ld 6x6 QFN L28.6x6 ISL6537CRZ ISL6537CRZ 0 to +70 28 Ld 6x6 QFN L28.6x6 VDDQ 7 15 FB (See Note) (Pb-free) 8 9 10 11 12 13 14 *Add -T suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN9142 Rev 6.00 Page 1 of 16 Jul 18, 2007 VDDQ LGATE DDR VTTSNS GND DRIVE2 UGATE FB2 BOOT VIDPGD PHASE VREF OUT S5 VREF IN OCSETISL6537 FN9142 Rev 6.00 Page 2 of 16 Jul 18, 2007 Block Diagram 5VSBY P12V S3 S5 FB COMP VDDQ P12V BOOT R GU EA4 EA1 DRIVE4 POR UGATE GMCH DUAL LDO R GL FB4 PWM REFADJ4 5VSBY P12V MONITOR AND CONTROL LGATE EA3 FAULT OSCILLATOR DRIVE3 250kHz SOFT-START & ENABLE A FB3 SOFT-START & ENABLE B SOFT-START & ENABLE C ENABLE VIDPGD PHASE ENABLE DDR VTT OCSET OC COMP P12V 20A VOLTAGE REFERENCE EA2 S3 0.800V DRIVE2 VTTSNS 0.680V (-15%) 0.920V (+15%) FB2 VDDQ(2) VTT REG VTT(2) UV/OV R U UV VREF IN UV/OV UV R L VREF OUT VIDPGD GND PAD GND(2)