DATASHEET ISL78225 FN7909 Rev 4.00 4-Phase Interleaved Boost PWM Controller with Light Load Efficiency September 5, 2014 Enhancement The ISL78225 4-phase controller is targeted for applications Features where high efficiency (>95%) and high power are required. The Peak current mode PWM control with adjustable slope multiphase boost converter architecture uses interleaved compensation timing to multiply channel ripple frequency and reduce input and output ripple. Lower ripple results in fewer input/output Precision resistor/DCR current sensing capacitors and therefore lower component cost and smaller 2-, 3- or 4-phase operation implementation area. Adjustable phase dropping/diode emulation/pulse skipping The ISL78225 has a dedicated pin to initiate the phase for high efficiency at light load dropping scheme for higher efficiency at light load by dropping Phase dropping facilitated with companion FET driver phases based on the load current, so the switching and core ISL78420 (featuring tri-level input control) losses in the converter are reduced significantly. As the load increases, the dropped phase(s) are added back to Adjustable switching frequency or external synchronization accommodate heavy load transients and improve efficiency. from 75kHz up to 1MHz per phase Over-temperature/overvoltage protection Input current is sensed continuously by measuring the voltage across a dedicated current sense resistor or inductor DCR. This 2V 1.0% internal reference current sensing provides precision channel-current balancing, Pb-free 44 Ld 10x10 EP-TQFP (RoHS compliant) and per-phase overcurrent protection. A separate totalizing current limit function provides overcurrent protection for all the -40C to +125C operating temperature range phases combined. This two-stage current protection provides AEC-Q100 qualified maximum performance and circuit reliability. Applications The ISL78225 can also provide for input voltage tracking via the VREF2 pin. The comparison reference voltage will be the lower Automotive power supplies of the VREF2 pin or the internal 2V reference. By using a resistor -Start/stop DC/DC converter network between VIN and VREF2 pin, the output voltage can - Electronic power steering systems (EPAS) track input voltage to limit the output power during automotive -Fuel pumps cranking conditions. - Injection system The ISL78225 can output a clock signal for expanding operation Audio trunk amplifier power supplies to 8 phases, which offers high system flexibility. The threshold-sensitive enable input is available to accurately Telecom and industrial power supplies coordinate the start-up of the ISL78225 with any other voltage rail. 0.98 WITH PHASE DROPPING WITHOUT PHASE DROPPING 0.93 0.88 0.83 0.78 16V INPUT, 36V OUTPUT SYNCHRONOUS BOOST 0.73 01234567 89 10 OUTPUT CURRENT (A) FIGURE 1. EFFICIENCY vs OUTPUT CURRENT vs PHASE DROPPING MODE FN7909 Rev 4.00 Page 1 of 22 September 5, 2014 EFFICIENCY (%)ISL78225 Pin Configuration ISL78225 (44 LD 10x10 EP-TQFP) TOP VIEW 44 43 42 41 40 39 38 37 36 35 34 FS 1 VIN 33 SS 2 DNC 32 3 DNC COMP 31 FB 4 ISEN4P 30 ISEN4N VREF2 5 29 GND 6 ISEN2P 28 SLOPE 7 27 ISEN2N PLL COMP 8 26 DNC SYNC 9 25 DNC 10 24 CLK OUT ISEN3P 11 23 ISEN3N PWM INV 12 13 14 15 16 17 18 19 20 21 22 Functional Pin Descriptions PIN SYMBOL DESCRIPTION 1 FS A resistor placed from FS to ground will set the PWM switching frequency. 2 SS Use this pin to set up the desired soft-start time. A capacitor placed from SS to ground will set up the soft-start ramp rate and in turn determine the soft-start time. 3 COMP The output of the transconductance amplifier. Place the compensation network between COMP and GND for compensation loop design. 4 FB The inverting input of the transconductance amplifier. A resistor network should be placed between the FB pin and output rail to set the output voltage. 5 VREF2 External reference input to the transconductance amplifier. When the VREF2 pin voltage drops below 1.8V, the internal reference will be shifted from 2V to VREF2. The VREF2 voltage can be programmed by connecting a resistor divider network from VCC or VIN. 6 GND Bias and reference ground for the IC. 7 SLOPE This pin programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to GND. Please refer to Adjustable Slope Compensation on page 18 for how to choose the resistor value. 8 PLL COMP This pin serves as the compensation node for the PLL. A second order passive loop filter connected between PLL COMP pin and GND compensates the PLL feedback loop. 9 SYNC Frequency synchronization pin. Connecting the SYNC pin to an external square pulse waveform (typically 20% to 80% duty cycle) will synchronize the converter switching frequency to the fundamental frequency of the input waveform. If SYNC function is not used, tie the SYNC pin to GND. A 500nA current source is connected internally to pull-down the SYNC pin if it is left open. 10 CLK OUT This pin provides a clock signal to synchronize with another ISL78225. This provides scalability and flexibility. The rising edge signal on the CLKOUT pin is in phase with the leading edge of the PWM1 signal. 11 PWM INV This pin determines the polarity of the PWM output signal. Pulling this pin to GND will force normal operation with inverting MOSFET drivers. Pulling this pin to VCC will invert the PWM signal for operation with non-inverting MOSFET drivers. This function provides the flexibility for the ISL78225 to work with different drivers. FN7909 Rev 4.00 Page 2 of 22 September 5, 2014 PWM TRI PGOOD EN PWM1 PWM3 DMAX VOUT OVB P COM PWM2 VOUT SEN VIN OVB PWM4 VIN SEN DNC DRIVE EN IOUT MODE DNC ISEN1N GND ISEN1P VCC