Features Datasheet R01DS0331EJ0100 RX72T Group Rev.1.00 Renesas MCUs Feb 08, 2019 200-MHz, 32-bit RX MCU, on-chip FPU, 1160 CoreMark, Supportive of 5V power supply, up to 1-MB flash memory, 128-KB SRAM, 32-KB data flash memory, 16-KB SRAM with ECC, Simultaneous sampling with 3 units of 12-bit A/D converter (up to 7 channels), Single-end/pseudo differential input supportive amplifier (6 channels), Analog comparator (6 channels), 200 MHz PWM (4 channels for 3-phase complementary, 2 channels for 5-phase complementary, 10 channels for single-phase complementary), 4-channel high-resolution PWM with resolution of 195 ps at the minimum, Host/function or OTG controller with full-speed USB 2.0 transfer, CAN, Encryption functions (optional) Features PLQP0144KA-B 20 20 mm, 0.5 mm pitch 32-bit RXv3 CPU core PLQP0100KB-B 14 14 mm, 0.5 mm pitch Maximum operating frequency: 200 MHz Capable of 1160 CoreMark in operation at 200 MHz JTAG and FINE (one-line) debugging interfaces A function for collectively saving the values of registers is available. Low-power design and architecture Operation from a single 2.7- to 5.5-V supply Various communications interfaces Four low-power modes Host/function or OTG controller (1 channel) with full-speed USB 2.0 (USBb) transfer On-chip code flash memory CAN (compliant with ISO11898-1), incorporating 32 mailboxes Supports versions with 1 Mbytes/512 Kbytes (1 channel) No wait cycles at up to 120 MHz or when the ROM cache is hit SCIj and SCIh with multiple functionalities (up to 6 channels) User code is programmable by on-board or off-board programming. Choose from among asynchronous mode, clock-synchronous mode, On-chip data flash memory 2 smart-card interface mode, simplified SPI, simplified I C, and 32 Kbytes, reprogrammable up to 100,000 times extended serial mode. Programming/erasing as background operations (BGOs) SCIi with 16-byte transmission and reception FIFOs (1 channel) 2 I C bus interface (RIICa) for transfer at up to 400 kbps (fast mode), On-chip SRAM, no wait states capable of SMBus operation (1 channel) 128Kbytes of SRAM (no wait states) RSPId (1 channel) for transfer at up to 30 Mbps 16 Kbytes of RAM with ECC (with wait) Up to 31 extended-function timers Data transfer 32-bit GPTW (10 channels): operation at 200 MHz, input capture, DMACa: 8 channels output compare, PWM waveforms: 10 output channels in single- DTCa: 1 channel phase complementary PWM mode/3 output channels in 3-phase ELC complementary PWM mode/2 output channels in 5-phase Module operation can be initiated by event signals without using complementary PWM mode, phase-counting mode, linkage with interrupts comparator (counting operation, PWM negate control) Linked operation between modules is possible when the CPU is in 16-bit MTU3d (9 channels): operation at 200 MHz, input capture, sleep mode output compare, PWM waveforms: 2 output channels in 3-phase complementary PWM mode, phase-counting mode Reset and supply management 8-bit TMR (8 channels) Power-on reset (POR) 16-bit CMT (4 channels) Low voltage detection (LVDA) with voltage settings High-resolution PWM waveform generation circuit Clock functions (HRPWM): 4 channels Frequency of resonator for main clock oscillator: 8 to 24 MHz (this Controlling the timing of rising or falling of the PWM output can be used as the PLL reference clock) waveform for 32-bit GPTW is realized with minimum of 195 ps High-speed on-chip oscillator: 16 MHz/18 MHz/20 MHz (this can resolution (in operation at 160 MHz) be used as the PLL reference clock) Low-speed on-chip oscillator: 240 kHz 12-bit A/D converter (S12ADH): Independent watchdog timer total of 30 channels for three units Up to three 12-bit units of sample-and-hold circuit included 120-kHz IWDT-dedicated on-chip oscillator clock operation Unit 0 (8 channels for 3 sample-and-hold circuits), Useful functions for IEC60730 compliance Unit 1 (8 channels for 3 sample-and-hold circuits), Oscillation-stoppage detection, functions for self-diagnosis and Unit 2 (14 channels) detection of disconnection for the A/D converter, clock frequency Programmable gain amplifier with pseudo differential amplification accuracy measurement circuit, independent watchdog timer, RAM (3 channels 2) test-assisting function by DOC, and CRCA, etc. Analog Comparator (CMPC): 6 channels Register write protection function can protect values in important registers against overwriting. 12-bit D/A converter: 2 channels Usable as a reference voltage for the analog comparator External bus Bus clock at 40 MHz (max) Temperature sensor for measuring temperature Four CS areas within the chip 8- or 16-bit bus space is selectable per area Encryption functions (Trusted Secure IP Lite) 128- or 256-bit key length of AES for ECB, CBC, GCM, others True random number generator Unauthorized access to the encryption engine is disabled and imposture and falsification of information are prevented Safe management of keys Up to 110 pins for general I/O ports 5-V tolerance, open drain, input pull-up, switchable driving ability Recommended operating temp. range (Topr) 40 C to +85 C 40 C to +105 C R01DS0331EJ0100 Rev.1.00 Page 1 of 176 Feb 08, 2019RX72T Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/9) Classification Module/Function Description CPU CPU Maximum operating frequency: 200 MHz 32-bit RX CPU (RXv3) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers 113 instructions Standard provided instructions: 111 Basic instructions: 77 Single precision floating point instructions: 11 DSP instructions: 23 Instructions for register bank save function: 2 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 32 64 bits On-chip divider: 32/32 32 bits Barrel shifter: 32 bits FPU Single-precision (32-bit) floating-point number Data types and floating-point exceptions in conformance with the IEEE754 standard Register bank save Fast collective saving and restoration of the values of CPU registers function 16 save register banks Memory Code flash memory Capacity: 1 Mbyte, 512 Kbytes ROM cache: Operation of an 8-Kbyte instruction fetching cache can be enabled or disabled (this is disabled by default). While ROM cache operation is enabled: - when the cache is hit, one-cycle access up to 200 MHz - when the cache is missed: one to two cycles if ICLK 120 MHz (bus wait: 0 cycles), two to three cycles if ICLK > 120 MHz (bus wait: 1 cycle). While ROM cache operation is disabled: one cycle if ICLK 120 MHz (bus wait: 0 cycles), two cycles if ICLK > 120 MHz (bus wait: 1 cycle). On-board programming: Five types Off-board programming (parallel programmer mode) The trusted memory (TM) function protects against the reading of programs from blocks 8 and 9. Data flash memory Capacity: 32 Kbytes Programming/erasing: 100,000 times Unique ID 12-byte unique ID for the device RAM Capacity: 128 Kbytes 200 MHz No-wait access SED (single error detection) RAM with ECC Capacity: 16 Kbytes 00FF C000h to 00FF FFFFh (16 Kbytes) SEC-DED (single error correction/double error detection) R01DS0331EJ0100 Rev.1.00 Page 2 of 176 Feb 08, 2019