X9410 Low Noise/Low Power/SPI Bus Data Sheet October 12, 2006 FN8193.2 DESCRIPTION Dual Digitally Controlled Potentiometer (XDCP) The X9410 integrates two digitally controlled potentiometers (XDCPs) on a monolithic CMOS FEATURES integrated circuit. Two potentiometers per package The digitally controlled potentiometer is implemented SPI serial interface using 63 resistive elements in a series array. Between Register oriented format each element are tap points connected to the wiper - Direct read/write/transfer wiper positions terminal through switches. The position of the wiper on - Store as many as four positions per the array is controlled by the user through the SPI potentiometer serial bus interface. Each potentiometer has Power supplies associated with it a volatile Wiper Counter Register -V = 2.7V to 5.5V CC (WCR) and four nonvolatile Data Registers (DR0:DR3) - V+ = 2.7V to 5.5V that can be directly written to and read by the user. The contents of the WCR controls the position of the - V- = -2.7V to -5.5V wiper on the resistor array through the switches. Low power CMOS Power-up recalls the contents of DR0 to the WCR. - Standby current < 1A - High reliability The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in - Endurance - 100,000 data changes per bit per a wide variety of applications including control, register parameter adjustments, and signal processing. - Register data retention - 100 years 8-bytes of nonvolatile EEPROM memory 10k resistor arrays Resolution: 64 taps each pot 24 Ld SOIC, 24 Ld TSSOP, and 24 Ld plastic DIP packages Pb-free plus anneal available (RoHS compliant) BLOCK DIAGRAM V CC Pot 0 V SS R0 R1 V /R H0 H0 Wiper V+ Counter Register V- (WCR) V /R R2 R3 L0 L0 HOLD CS V /R W0 W0 SCK Interface SO and SI Control 8 Circuitry A0 V /R A1 W1 W1 Pot 1 Data WP R0 R1 Wiper V /R H1 H1 Resistor Counter Array Register Pot1 (WCR) R2 R3 V /R L1 L1 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT X9418, ISL22424X9410 Ordering Information POTENTIOMETER V LIMITS ORGANIZATION TEMP RANGE CC PART NUMBER PART MARKING (V) (k ) (C) PACKAGE PKG. DWG. X9410YS24I X9410YS I 5 10% 2.5 -40 to 85 24 Ld SOIC (300 mil) M24.3 X9410YS24IZ (Note) X9410YS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9410WP24I X9410WP I 10 -40 to 85 24 Ld PDIP E24.6 X9410WS24I* X9410WS I -40 to 85 24 Ld SOIC (300 mil) M24.3 X9410WS24IZ* (Note) X9410WS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9410WV24I* X9410WV I -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9410WV24IZ* (Note) X9410WV ZI -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9410YS24I-2.7 X9410YS G 2.7 to 5.5 2.5 -40 to 85 24 Ld SOIC (300 mil) M24.3 X9410YS24IZ-2.7 (Note) X9410YS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9410WP24I-2.7 X9410WP G 10 -40 to 85 24 Ld PDIP E24.6 X9410WS24I-2.7* X9410WS G -40 to 85 24 Ld SOIC (300 mil) M24.3 X9410WS24IZ-2.7* (Note) X9410WS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 X9410WV24-2.7* X9410WV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044 X9410WV24Z-2.7* (Note) X9410WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9410WV24I-2.7* X9410WV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044 X9410WV24IZ-2.7* (Note) X9410WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 *AddT1 suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PIN DESCRIPTIONS in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is Host Interface Pins required prior to the start of any operation. Serial Output (SO) Hold (HOLD) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked HOLD is used in conjunction with the CS pin to select out by the falling edge of the serial clock. the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause Serial Input the serial communication with the controller without resetting the serial sequence. To pause, HOLD must SI is the serial data input pin. All opcodes, byte be brought LOW while SCK is LOW. To resume addresses and data to be written to the pots and pot communication, HOLD is brought HIGH, again while registers are input on this pin. Data is latched by the SCK is LOW. If the pause feature is not used, HOLD rising edge of the serial clock. should be held HIGH at all times. Serial Clock (SCK) Device Address (A - A ) 0 1 The SCK input is used to clock data into and out of the The address inputs are used to set the least significant X9410. 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Chip Select (CS) address input in order to initiate communication with When CS is HIGH, the X9410 is deselected and the the X9410. A maximum of 4 devices may occupy the SO pin is at high impedance, and (unless an internal SPI serial bus. write cycle is underway) the device will be in the standby state. CS LOW enables the X9410, placing it FN8193.2 2 October 12, 2006