LVDS Interface ICs 27bit LVDS Transmitter BU90T81 General Description Key Specifications The BU90T81 transmitter operates from 20MHz to Supply Voltage range 1.65 to 1.95 V 112MHz wide clock range, and 27bits data of parallel Operating frequency 20 to 112MHz LVCMOS level inputs(R/G/B24bits and VSYNC,HSYNC,DE) Operating Temperature Range 20 to 85 are converted to four channels of LVDS data stream. Data is Power Consumption 50mW(Typ) transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The BU90T81 operates from a single 1.8V supply for low Packages power. And the BU90T81 has low swing mode to be able to expect further low power and low EMI . VBGA048W040 4.004.00 0.90 Features Applications 24bits data of parallel LVCMOS level inputs are Tablet converted to four channels of LVDS data stream. Netbook PC Support clock frequency from 20MHz up to 112MHz. Digital Picture Frame Low power 1.8V CMOS design Power down mode Clock edge selectable Support 6bit/8bit mode selectable Support reduced swing LVDS for low EMI. Support LVDS Outputs pin reverse function Support spread spectrum clock generator input Block Diagram LVCMOS Input LVDS Output TCLK +/- CLKIIN PLL (20-112MHz) (20-112MHz) 8 R 7:0 TA +/- 8 G 7:0 TB +/- 8 B 7:0 Parallel to Serial HSYNC TC +/- VSYNC DE TD +/- FLIP 6B8B RS 1:0 RF XRST Figure-1 Block Diagram Product structureSilicon monolithic integrated circuit This product is not designed protection against radioactive rays www.rohm.com TSZ02201-0L2L0V100010-1-2 2012 ROHM Co., Ltd. All rights reserved. 1/11 23.JAN.2012 Rev.001 TSZ2211114001 DatasheetDatasheet BU90T81 Pin Configuration Top view 12 345 67 A G 5 G 7 R 1 R 3 R 5 R 6 R 7 B - G 6 R 0 R 2 R 4 TA- TA+ C G 3 G 4 GND RS 1 R S 0 TB- TB+ D G 1 G 2 RF VDD VD D TC - TC + E G 0 B 7 FLIP 6B8B GND TC LK- TC LK+ F B 6 B 5 B 2 B 0 D E TD - TD + G B 4 B 3 B 1 HS YNC VS YNC C L KIN XR S T 48pin VBGA Figure-2 Pin Diagram (Top View) Pin Description Pin Name Pin No. Type Descriptions TA+/-, TB+/-, B7,B6,C7,C6,D7,D6,F7,F6 LVDS Data out LVDS TC+/-,TD+/- OUT TCLK+/- E7,6 LVDS Clock out R 7:0 A7,A6,A5,B5,A4,B4,A3,B3 G 7:0 A2,B2,A1,C2,C1,D2,D1,E1 Pixel and control data inputs CMOS B 7:0 E2,F1,F2,G1,G2,F3,G3,F4 IN HSYNC,VSYNC, G4,G5,F5 DE CLKIN G6 Clock input Power Down XRST G7 HNormal operation LPower down ( all LVDS output signal are Hi-z) Input CLK Triggering Edge Select. RF D3 HRising edge LFalling edge LVDS swing mode select RS1 RS0 LVDS swing L L TYP=160V RS 1:0 C3,C5 CMOS L H TYP=200V IN H L TYP=350V H H Reserved 6bit/8bit mode select H : 6bit mode(FLIP=L TD+/- is Hiz) 6B8B E4 (FLIP=H TA+/- is Hiz) L : 8bit mode LVDS output pin reverse select. FLIP E3 H : Reverse L : Normal VDD D4,D5 POWER 1.8V Power supply GND C3,E5 GND Ground Pins www.rohm.com TSZ02201-0L2L0V100010-1-2 2/11 2012 ROHM Co., Ltd. All rights reserved. 23.JAN.2012 Rev.001 TSZ2211115001