FEDL62Q1500-05 Issue Date: Mar 19, 2020 ML62Q1500/1800 Group 16-bit micro controller GENERAL DESCRIPTION ML62Q1500/1800 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the multiplier/divider, CRC generator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports, UART, 2 Synchronous serial port, I C bus interface unit (Master, Slave), Buzzer, Voltage Level Supervisor(VLS), Successive approximation type A/D converter, D/A converter , Analog comparator, Safety function(IEC60730/60335 Class B) and so on. The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel processing. The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming) function supports the Flash programming in production line. The ML62Q1500/1800 Group has seven packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte). Table 1 ML62Q1500/1800 Group Product List 48pin 52pin 64pin 80pin 100pin Program Data memory Data Flash TQFP52 TQFP48 QFP64 QFP80 QFP100 memory (RAM) TQFP64 TQFP100 512Kbyte ML62Q1859 ML62Q1869 ML62Q1879 32Kbyte 8Kbyte 384Kbyte ML62Q1858 ML62Q1868 ML62Q1878 256Kbyte ML62Q1557 ML62Q1567 ML62Q1577 192Kbyte 16Kbyte ML62Q1556 ML62Q1566 ML62Q1576 160Kbyte ML62Q1555 ML62Q1565 ML62Q1575 16Kbyte ML62Q1564 ML62Q1574 128Kbyte 8Kbyte ML62Q1534 ML62Q1544 ML62Q1554 4Kbyte 16Kbyte ML62Q1563 ML62Q1573 96Kbyte 8Kbyte ML62Q1533 ML62Q1543 ML62Q1553 64Kbyte ML62Q1532 ML62Q1542 ML62Q1552 48Kbyte 8Kbyte ML62Q1531 ML62Q1541 ML62Q1551 32Kbyte ML62Q1530 ML62Q1540 ML62Q1550 FEATURES CPU 16-bit RISC CPU: nX-U16/100(A35 core) Instruction system: 16-bit length instructions Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on Built-in On-chip debug function Built-in ISP (In-System Programming) function Minimum instruction execution time Approximately 30.5 s (at 32.768 kHz system clock) Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock) 1/70 FEDL62Q1500-05 Coprocessor for multiplication and division Multiplication : 16bit 16bit (operation time : 4 cycles) Division : 32bit 16bit (operation time : 8 cycles) Division : 32bit 32bit (operation time : 16 cycles) Multiply-accumulate (non-saturating): 16bit 16bit + 32bit (operation time : 4 cycles) Multiply-accumulate (saturating): 16bit 16bit + 32bit (operation time : 4 cycles) Signed or Unsigned is selectable Operating voltage and temperature = 1.6 to 5.5 V (V should be 1.8V or over at Power-on) Operating voltage: V DD DD Operating temperature: -40 C to +105 C Internal memory Program memory area Rewrite count: 100 cycles Write unit: 32bit(4byte) Erase unit: 16Kbyte/1Kbyte Erase/Write temperature: 0 C to +40 C Data Flash memory area Rewrite count 10,000 cycles Write unit: 8bit(1byte) Erase unit: all area/128byte Erase/Write temperature: -40 C to +85 C Back Ground Operation(CPU can work while erasing and rewriting) This product uses Super Flash technology licensed from Silicon Storage Technology, Inc. Super Flash is a registered trademark of Silicon Storage Technology, Inc. Data RAM area Rewrite unit: 8bit/16bit (1byte/2byte) Parity check function is available (interrupt / reset are generatable at Parity error) Clock Generation Circuit Low-speed clock (LSCLK) Internal low-speed RC oscillation: Approximately 32.768 kHz External low-speed clock input: Approximately 32.768 kHz External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable 3 selectable crystal oscillation mode (Tough, Normal, and Low current consumption) Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins Normal mode: Normal oscillation allowance and current consumption Low current consumption mode: Smallest oscillation allowance to make lower current consumption High-speed clock (HSCLK) PLL oscillation: 2 selectable oscillation frequency (24MHz and 16MHz) by code option Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1kHz) Reset Reset by reset input pin Reset by Power-On Reset Reset by WDT overflow Reset by WDT invalid clear Reset by RAM parity error Reset by unused ROM area access (instruction access) Reset by voltage level supervisor (VLS) Software reset by BRK instruction (reset CPU only) Reset the peripherals individually Collective reset to the all control pins and peripheral circuits 2/70