GS9091BCBE3

GS9091B GenLINX II 270Mb/s Deserializer for SDI and DVB-ASI Key Features Description SMPTE 259M-C compliant descrambling and NRZI to The GS9091B is a 270Mb/s equalizing and reclocking dese- NRZ decoding (with bypass) rializer with an internal FIFO. It provides a complete re- ceive solution for SD-SDI and DVB-ASI applications. DVB-ASI 8b/10b decoding Integrated Cable Equalizer In addition to equalizing, reclocking and deserializing the input data stream, the GS9091B performs NRZI -to-NRZ de- 500m typical equalization of Belden 1694A cable coding, descrambling as per SMPTE 259M-C, and word Integrated line-based FIFO for data alignment/delay, alignment when operating in SMPTE mode. When operat- clock phase interchange, DVB-ASI data packet ing in DVB-ASI mode, the device will word align the data to extraction and clock rate interchange, and ancillary K28.5 sync characters and 8b/10b decode the received data packet extraction stream. Integrated VCO and reclocker The integrated equalizer is optimized for 270Mb/s and can User selectable additional processing features typically equalize up to 500m of Belden 1694A cable. Both including: the equalizer and the internal reclocker are fully compati- TRS, ANC data checksum, and EDH CRC error ble with both SMPTE and DVB-ASI input streams. detection and correction The GS9091B includes a range of data processing functions programmable ANC data detection such as EDH support (error detection and handling), and illegal code remapping automatic standards detection. The device can also detect Internal flywheel for noise immune H, V, F extraction and extract SMPTE 352M payload identifier packets and in- dependently identify the received video standard. This in- Automatic standards detection and indication formation is read from internal registers via the host Enhanced Gennum Serial Peripheral Interface (GSPI) interface port. JTAG test interface The GS9091B also incorporates a video line-based FIFO. Polarity insensitive for DVB-ASI and SMPTE signals This FIFO may be used in four user-selectable modes to car- +1.8V core power supply with optional +1.8V or +3.3V ry out tasks such as data alignment / delay, clock phase in- I/O power supply terchange, MPEG packet extraction and clock rate Small footprint (11mm x 11mm) interchange, and ancillary data packet extraction. Low power operation (typically 350mW) Parallel data outputs are provided in 10-bit multiplexed Pb-free and RoHS compliant format, with the associated parallel clock output signal op- erating at 27MHz. Applications The device may also be used in a low-latency data pass SMPTE 259M-C Serial Digital Interfaces through mode where only descrambling and word align- DVB-ASI Serial Digital Interfaces ment will be performed in SMPTE mode. GS9091B GenLINX II 270Mb/s Deserializer for SDI 1 of 73 www.semtech.com and DVB-ASI Final Data Sheet Proprietary & Confidential 38910 - 3 February 2013RD RESET RD CLK IOPROC EN STAT 3:0 FW EN JTAG EN CS TMS SCLK TCK SMPTE sync detect SDIN TDI DVB ASI SDOUT TDO ASI sync detect SMPTE BYPASS AUTO/MAN LOCKED RESET PCLK LF- LF+ LB CONT EQ BYPASS Functional Block Diagram carrier detect Programmable I/O LOCK detect pll lock SMPTE De- DOUT 9:0 scramble, Word Alignment and Flywheel TRS Correct TRS Check DATA ERROR CSUM Correct CSUM Check DDI EDH Check & FIFO Equalizer Reclocker ANC Data S->P Correct DDI Detection DVB-ASI Illegal Code Re- Word Alignment map and 8b/10b Decode Power HOST Interface On / JTAG test Reset GS9091B Functional Block Diagram GS9091B GenLINX II 270Mb/s Deserializer for SDI 2 of 73 and DVB-ASI Final Data Sheet Proprietary & Confidential 38910 - 3 February 2013