SX1213IWLTRT

SX1213 Receiver Ultra-Low Power Integrated UHF Receiver ADVANCED COMMUNICATIONS & SENSING General Description Features The SX1213 is a low cost single-chip receiver Low Rx power consumption: 3mA operating in the frequency ranges from 300MHz to Good reception sensitivity: down to -104 dBm at 510MHz. The SX1213 is optimized for very low power 25 kb/s in FSK, -110 dBm at 2kb/s in OOK consumption (3mA). It incorporates a baseband Packet handling feature with data whitening and demodulator with data rates up to 200 kb/s. Data CRC processing handling features include a sixty-four byte FIFO, RSSI (Received Signal Strength Indicator) range packet handling, CRC and data whitening processing. from Rx noise floor to 0 dBm Its highly integrated architecture allows for minimum Bit rates up to 200 kb/s, NRZ coding external component count whilst maintaining design On-chip frequency synthesizer flexibility. All major RF communication parameters are FSK and OOK modulation programmable and most of them may be dynamically Incoming sync word recognition set. It complies with European (ETSI EN 300-220 Built-in Bit-Synchronizer for incoming data and V2.1.1) and North American (FCC part 15.247 and clock synchronization and recovery 15.249) regulatory standards. 5 x 5 mm TQFN package Optimized Circuit Configuration for Low-cost applications Ordering Information Pin to pin compatible with SX1212 Transceiver Table 1: Ordering Information Applications Minimum Order Part number Delivery Quantity / Multiple Wireless alarm and security systems Wireless sensor networks SX1213IWLTRT Tape & Reel 3000 pieces Automated Meter Reading Home and building automation TQFN-32 package Operating range -40 +85C Industrial monitoring and control T refers to Lead Free packaging Remote Wireless Control This device is WEEE and RoHS compliant Application Circuit Schematic st Rev.2 July 1 , 2009 Page 1 of 65 www.semtech.com SX1213 ADVANCED COMMUNICATIONS & SENSING Table of Contents 1. General Description ................................................................... 5 5.3.1. General Description .................................................36 1.1. Simplified Block Diagram................................................... 5 5.3.2. Rx Processing ..........................................................37 5.3.3. Interrupt Signals Mapping ........................................37 1.2. Pin Diagram....................................................................... 6 1.3. Pin Description................................................................... 7 5.3.4. uC Connections........................................................38 2. Electrical Characteristics............................................................ 8 5.3.5. Continuous Mode Example ......................................38 2.1. ESD Notice ........................................................................ 8 5.4. Buffered Mode ..................................................................39 2.2. Absolute Maximum Ratings............................................... 8 5.4.1. General Description .................................................39 5.4.2. Rx Processing ..........................................................39 2.3. Operating Range ............................................................... 8 2.4. Chip Specification.............................................................. 8 5.4.3. Interrupt Signals Mapping ........................................40 2.4.1. Power Consumption.................................................. 8 5.4.4. uC Connections........................................................41 2.4.2. Frequency Synthesis................................................. 9 5.4.5. Buffered Mode Example...........................................41 2.4.3. Receiver .................................................................. 10 5.5. Packet Mode.....................................................................42 5.5.1. General Description .................................................42 2.4.4. Digital Specification................................................. 11 3. Architecture Description........................................................... 12 5.5.2. Packet Format..........................................................42 3.1. Power Supply Strategy .................................................... 12 5.5.3. Rx Processing ..........................................................44 3.2. Frequency Synthesis Description .................................... 13 5.5.4. Packet Filtering ........................................................44 3.2.1. Reference Oscillator................................................ 13 5.5.5. DC-Free Data Mechanisms......................................46 5.5.6. Interrupt Signal Mapping ..........................................47 3.2.2. CLKOUT Output...................................................... 13 3.2.3. PLL Architecture...................................................... 14 5.5.7. uC Connections........................................................47 3.2.4. PLL Tradeoffs.......................................................... 14 5.5.8. Packet Mode Example .............................................48 3.2.5. Voltage Controlled Oscillator................................... 15 5.5.9. Additional Information ..............................................48 3.2.6. PLL Loop Filter........................................................ 16 6. Configuration and Status Registers ..........................................49 6.1. General Description..........................................................49 3.2.7. PLL Lock Detection Indicator .................................. 16 3.2.8. Frequency Calculation ............................................ 16 6.2. Main Configuration Register - MCParam..........................49 3.3. Receiver Description........................................................ 18 6.3. Interrupt Configuration Parameters - IRQParam ..............51 3.3.1. Architecture ............................................................. 18 6.4. Receiver Configuration parameters - RXParam...............53 3.3.2. LNA and First Mixer ................................................ 19 6.5. Sync Word Parameters - SYNCParam.............................54 6.6. Oscillator Parameters - OSCParam .................................55 3.3.3. IF Gain and Second I/Q Mixer................................. 19 3.3.4. Channel Filters ........................................................ 19 6.7. Packet Handling Parameters PKTParam ......................56 3.3.5. Channel Filters Setting in FSK Mode ...................... 20 7. Application Information .............................................................57 3.3.6. Channel Filters Setting in OOK Mode ..................... 21 7.1. Crystal Resonator Specification .......................................57 3.3.7. RSSI........................................................................ 21 7.2. Software for Frequency Calculation .................................57 7.2.1. GUI...........................................................................57 3.3.8. Fdev Setting in Receive Mode ................................ 23 3.3.9. FSK Demodulator.................................................... 23 7.2.2dll for Automatic Production Bench.........................57 3.3.10. OOK Demodulator................................................. 23 7.3. Switching Times and Procedures .....................................57 3.3.11. Bit Synchronizer .................................................... 26 7.3.1. Optimized Receive Cycle .........................................58 3.3.12. Alternative Settings ............................................... 27 7.3.2. Receiver Frequency Hop Optimized Cycle ..............59 7.4. Reset of the Chip..............................................................60 3.3.13. Data Output........................................................... 27 4. Operating Modes...................................................................... 28 7.4.1. POR .........................................................................60 4.1. Modes of Operation ......................................................... 28 7.4.2. Manual Reset ...........................................................60 4.2. Digital Pin Configuration vs. Chip Mode .......................... 28 7.5. Reference Design.............................................................61 5. Data Processing....................................................................... 29 7.5.1. Application Schematic..............................................61 5.1. Overview.......................................................................... 29 7.5.2. PCB Layout ..............................................................61 5.1.1. Block Diagram......................................................... 29 7.5.3. Bill Of Material..........................................................62 5.1.2. Data Operation Modes ............................................ 29 7.5.4. Ordering Information for Tools .................................63 5.2. Control Block Description ................................................ 30 8. Packaging Information ..............................................................63 5.2.1. SPI Interface ........................................................... 30 8.1. Package Outline Drawing .................................................63 5.2.2. FIFO ........................................................................ 32 8.2. PCB Land Pattern.............................................................64 5.2.3. Sync Word Recognition........................................... 34 8.3. Tape & Reel Specification ................................................64 5.2.4. Packet Handler........................................................ 35 9. Revision History ........................................................................65 5.2.5. Control..................................................................... 35 10. Contact Information.................................................................65 5.3. Continuous Mode ............................................................ 36 st Rev.2 July 1 , 2009 Page 2 of 65 www.semtech.com