SX1239 WIRELESS & SENSING DATASHEET SX1239 Receiver Low Power Integrated UHF Receiver VBAT1&2 VR ANA VR DIG RC Power Distribution System Oscillator / LNA Modulators Single to Mixers Differential RFIN RESET SPI RSSI AFC GND Division by 2, 4 or 6 DIO0 Tank DIO1 Inductor DIO2 Loop Frac-N PLL NC Filter DIO3 Synthesizer DIO4 NC DIO5 XO NC 32 MHz XTAL GND GENERAL DESCRIPTION KEY PRODUCT FEATURES The SX1239 is a highly integrated RF receiver capable of High Sensitivity: down to -120 dBm at 1.2 kbps operation over a wide frequency range, including the 433, High Selectivity: 16-tap FIR Channel Filter 868 and 915 MHz license-free ISM (Industry Scientific and Medical) frequency bands. Its highly integrated architecture Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, allows for a minimum of external components whilst 80 dB Blocking Immunity, no Image Frequency response maintaining maximum design flexibility. All major RF Low current: Rx = 16 mA, 100nA register retention communication parameters are programmable and most of Constant RF performance over voltage range of chip them can be dynamically set. The SX1239 offers the unique advantage of programmable narrow-band and wide-band FSK Bit rates up to 300 kb/s communication modes without the need to modify external Fully integrated synthesizer with a resolution of 61 Hz components. The SX1239 is optimized for low power consumption while offering high sensitivity and channelized FSK, GFSK, MSK, GMSK and OOK demodulation operation. TrueRF technology enables a low-cost external Built-in Bit Synchronizer performing Clock Recovery component count (elimination of the SAW filter) whilst still Incoming Sync Word Recognition satisfying ETSI and FCC regulations. 115 dB+ Dynamic Range RSSI APPLICATIONS Automatic RF Sense with ultra-fast AFC Packet engine with CRC, AES-128 encryption and 66- Automated Meter Reading byte FIFO Wireless Sensor Networks Built-in temperature sensor and Low Battery indicator Home and Building Automation Wireless Alarm and Security Systems ORDERING INFORMATION Industrial Monitoring and Control Wireless M-BUS Part Number Delivery MOQ / Multiple SX1239IMLTRT Tape & Reel 3000 pieces MARKETS Europe: EN 300-220-1 QFN 24 Package - Operating Range -40 +85C North America: FCC Part 15.247, 15.249, 15.231 Pb-free, Halogen free, RoHS/WEEE compliant product Narrow Korean and Japanese bands Revision 7 - July 2013 Page 1 www.semtech.com 2013 Semtech Corporation Decimation and & Filtering Demodulator & Bit Synchronizer Packet Engine & 66 Bytes FIFO Control Registers - Shift Registers - SPI InterfaceSX1239 WIRELESS & SENSING DATASHEET Table of contents Section Page 1. General Description ................................................................................................................................................. 8 1.1. Simplified Block Diagram ................................................................................................................................. 8 1.2. Pin and Marking Diagram ................................................................................................................................9 1.3. Pin Description ...............................................................................................................................................10 2. Electrical Characteristics ....................................................................................................................................... 11 2.1. ESD Notice .................................................................................................................................................... 11 2.2. Absolute Maximum Ratings ........................................................................................................................... 11 2.3. Operating Range............................................................................................................................................ 11 2.4. Chip Specification ..........................................................................................................................................12 2.4.1. Power Consumption.................................................................................................................................. 12 2.4.2. Frequency Synthesis................................................................................................................................. 12 2.4.3. Receiver .................................................................................................................................................... 13 2.4.4. Digital Specification................................................................................................................................... 14 3. Chip Description .................................................................................................................................................... 15 3.1. Power Supply Strategy .................................................................................................................................. 15 3.2. Low Battery Detector ..................................................................................................................................... 15 3.3. Frequency Synthesis ..................................................................................................................................... 15 3.3.1. Reference Oscillator.................................................................................................................................. 15 3.3.2. CLKOUT Output ........................................................................................................................................16 3.3.3. PLL Architecture........................................................................................................................................ 16 3.3.4. Lock Time ..................................................................................................................................................17 3.3.5. Lock Detect Indicator................................................................................................................................. 17 3.4. Receiver Description...................................................................................................................................... 17 3.4.1. Block Diagram........................................................................................................................................... 17 3.4.2. LNA - Single to Differential Buffer .............................................................................................................18 3.4.3. Automatic Gain Control ............................................................................................................................. 18 3.4.4. Continuous-Time DAGC............................................................................................................................ 20 3.4.5. Quadrature Mixer - ADCs - Decimators .................................................................................................... 20 3.4.6. Channel Filter............................................................................................................................................ 20 3.4.7. DC Cancellation ........................................................................................................................................22 3.4.8. Complex Filter - OOK................................................................................................................................ 22 3.4.9. RSSI.......................................................................................................................................................... 22 3.4.10. Cordic...................................................................................................................................................... 23 3.4.11. Bit Rate Setting ....................................................................................................................................... 23 3.4.12. FSK Demodulator.................................................................................................................................... 24 3.4.13. OOK Demodulator ...................................................................................................................................25 3.4.14. Bit Synchronizer ......................................................................................................................................27 3.4.15. Frequency Error Indicator........................................................................................................................ 27 3.4.16. Automatic Frequency Correction............................................................................................................. 28 Revision 7 - July 2013 Page 2 www.semtech.com 2013 Semtech Corporation