Si515 VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 100 kHZ TO 250 MHZ Features Supports any frequency from Optional integrated 1:2 CMOS Si5602 100 kHz to 250 MHz fanout buffer Low-jitter operation 3.3 and 2.5 V supply options Short lead times: <2 weeks Industry-standard 5x7, 3.2x5, and AT-cut fundamental mode crystal 2.5x3.2 mm packages 5X7MM, 3.2X5MM 2.5X3.2MM ensures high reliability/low aging Pb-free/RoHS-compliant High power supply noise rejection Selectable Kv (60, 90, 120, 1% control voltage linearity 150 ppm/V) Ordering Information: Available CMOS, LVPECL, LVDS, See page 14. and HCSL outputs Applications Pin Assignments: SONET/SDH/OTN Broadcast video See page 12. PON Telecom Low Jitter PLLs Switches/routers xDSL FPGA/ASIC clock generation 1 6 V Vc DD Description 2 5 NC OE The Si515 VCXO utilizes Silicon Laboratories advanced PLL technology to 3 CLK GND 4 provide any frequency from 100 kHz to 250 MHz. Unlike a traditional VCXO where a different crystal is required for each output frequency, the Si515 uses one fixed crystal and Silicon Labs proprietary synthesizer to generate any frequency across CMOS VCXO this range. This IC-based approach allows the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. In 1 V 6 Vc DD addition, this solution provides superior control voltage linearity and supply noise rejection, improving PLL stability and simplifying low jitter PLL design in noisy 2 5 OE CLK environments. The Si515 is factory-configurable for a wide variety of user specifications, including frequency, supply voltage, output format, tuning slope and 3 4 CLK+ GND stability. Specific configurations are factory-programmed at time of shipment, LVPECL/LVDS/HCSL/ eliminating long lead times and non-recurring engineering charges associated with Dual CMOS VCXO custom frequency oscillators. Functional Block Diagram V DD Power Supply Filtering OE Fixed Any-Frequency CLK+ Frequency 0.1 to 250 MHz Oscillator Clock Synthesis CLK Vc ADC GND Rev. 1.2 6/18 Copyright 2018 by Silicon Laboratories Si515Si515 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages 11 3. Pin Descriptions .12 3.1. Dual CMOS Buffer 13 4. Ordering Information .14 5. Package Outline Diagram: 5 x 7 mm, 6-pin .15 6. PCB Land Pattern: 5 x 7 mm, 6-pin 16 7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin 17 8. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin .18 9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin 19 10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin 21 11. Top Marking .22 11.1. Si515 Top Marking .22 11.2. Top Marking Explanation 22 Document Change List .23 2 Rev. 1.2