Si532 REVISION D DUAL FREQUENCY CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ) Features Si5602 Available with any-frequency output Internal fixed crystal frequency frequencies from 10 MHz to 945 MHz ensures high reliability and low and select frequencies to 1.4 GHz aging Two selectable output frequencies Available CMOS, LVPECL, LVDS, and CML outputs 3rd generation DSPLL with superior 3.3, 2.5, and 1.8 V supply options jitter performance Industry-standard 5 x 7 mm 3x better frequency stability than package and pinout SAW-based oscillators Pb-free/RoHS-compliant Ordering Information: Applications See page 7. SONET/SDH Test and measurement Networking Clock and data recovery Pin Assignments: SD/HD video FPGA/ASIC clock generation See page 6. Description (Top View) The Si532 dual frequency XO utilizes Silicon Laboratories advanced DSPLL circuitry to provide a low jitter clock at high frequencies. The Si532 is 1 6 V FS DD available with any-frequency output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is OE 2 5 CLK required for each output frequency, the Si532 uses one fixed crystal frequency to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency GND 3 4 CLK+ stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in (LVDS/LVPECL/CML) noisy environments typically found in communication systems. The Si532 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. V 1 6 DD FS Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. OE 2 5 NC Functional Block Diagram GND 3 4 CLK V CLK CLK+ DD (CMOS) Any-frequency Fixed 101400 MHz Frequency DSPLL XO Clock Synthesis FS OE GND Rev. 1.3 4/13 Copyright 2013 by Silicon Laboratories Si532Si532 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Units 1 V 3.3 V option 2.97 3.3 3.63 V Supply Voltage DD 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Supply Current I Output enabled DD LVPECL 121 111 CML 99 108 mA 90 LVDS 98 81 CMOS 88 Tristate mode 60 75 mA Output Enable (OE) V 0.75 x V V IH DD 2 and Frequency Select (FS) V 0.5 V IL Operating Temperature Range T 40 85 C A Notes: 1. Selectable parameter specified by part number. See Section 3.Ordering Informatio on page 7 for further details. 2. OE and FS pins include a 17 k pullup resistor to V . Pulling OE to ground causes outputs to tristate. DD Table 2. CLK Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Units 1,2 f LVPECL/LVDS/CML 10 945 MHz Nominal Frequency O CMOS 10 160 MHz Initial Accuracy Measured at +25 C at time of f 1.5 ppm i shipping 1,3 Temperature Stability 7 +7 20 +20 ppm 50 +50 Aging Frequency drift over first year 3 ppm f a Frequency drift over 20 year life 10 ppm Total Stability Temp stability = 7 ppm 20 ppm Temp stability = 20 ppm 31.5 ppm Temp stability = 50 ppm 61.5 ppm Notes: 1. See Section 3.Ordering Informatio on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to f . O 2 Rev. 1.3