570ECB000118DG Silicon Labs

Si570/Si571 2 10 MHZ TO 1.4 GHZ I C PROGRAMMABLE XO/VCXO Features Any programmable output Internal fixed crystal frequency frequencies from 10 to 945 MHz and ensures high reliability and low Si5602 select frequencies to 1.4 GHz aging 2 Available LVPECL, CMOS, I C serial interface LVDS, and CML outputs 3rd generation DSPLL with superior Industry-standard 5x7 mm jitter performance package 3x better frequency stability than Pb-free/RoHS-compliant SAW-based oscillators 1.8, 2.5, or 3.3 V supply Applications Ordering Information: SONET/SDH High performance See page 32. xDSL instrumentation 10 GbE LAN/WAN Low-jitter clock generation ATE Optical modules Pin Assignments: Clock and data recovery See page 31. Description (Top View) The Si570 XO/Si571 VCXO utilizes Silicon Laboratories advanced DSPLL SDA circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user- 7 programmable to any output frequency from 10 to 945 MHz and select frequencies 2 NC 1 6 V to 1400 MHz with <1 ppb resolution. The device is programmed via an I C serial DD interface. Unlike traditional XO/VCXOs where a different crystal is required for each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL OE 2 5 CLK clock synthesis IC to provide any-frequency operation. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise GND 3 4 CLK+ rejection, simplifying the task of generating low-jitter clocks in noisy environments 8 typically found in communication systems. SCL Functional Block Diagram Si570 CLK- CLK+ V DD SDA 7 OE V C 1 6 V DD 10-1400 MHz Fixed Frequency DSPLL Clock SDA XO Synthesis SCL OE 2 5 CLK Si571 only GND 3 4 CLK+ ADC 8 SCL GND Si571 V C Rev. 1.5 4/14 Copyright 2014 by Silicon Laboratories Si570/Si571Si570/Si571 2 Rev. 1.5