CY2SSTV857-27 CY2SSTV857-27 Differential Clock Buffer/Driver DDR333/PC2700-Compliant Features Description Operating frequency: 60 MHz to 200 MHz The CY2SSTV857-27 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential Supports 266, 333 MHz DDR SDRAM clocks in high-speed applications. The CY2SSTV857-27 10 differential outputs from 1 differential input generates ten differential pair clock outputs from one differ- ential pair clock input. In addition, the CY2SSTV857-27 Spread-Spectrum-compatible features differential feedback clock outputs and inputs. This Low jitter (cycle-to-cycle): < 75 allows the CY2SSTV857-27 to be used as a zero-delay buffer. Very low skew: < 100 ps When used as a zero-delay buffer in nested clock trees, the Power management control input CY2SSTV857-27 locks onto the input reference and translates with near-zero delay to low-skew outputs. High-impedance outputs when input clock < 10 MHz 2.5V operation Pin-compatible with CDC857-2 and -3 48-pin TSSOP package Industrial temp. of 40 to +85C Conforms to JEDEC DDR specification Block Diagram Pin Configuration 3 Y0 VSS 1 48 VSS 2 Y0 Y0 2 47 Y5 5 Y1 37 T est and Y0 3 46 Y5 PD 6 Y1 Powerdown VDDQ 4 45 VDDQ 10 16 Logic Y2 AVDD Y1 5 44 Y6 9 Y2 Y1 6 43 Y6 20 Y3 VSS 7 42 VSS 19 Y3 VSS 8 41 VSS 22 Y4 Y2 9 40 Y7 23 Y4 Y2 10 39 Y7 46 Y5 VDDQ 11 38 VDDQ 47 Y5 VDDQ 12 37 PD 44 CLK 13 36 FBIN Y6 43 Y6 CLK 14 35 FBIN 13 CLK 39 VDDQ 15 34 VDDQ Y7 14 CLK 40 Y7 AVDD 16 33 FBOUT PLL 29 AVSS 17 32 FBOUT 36 Y8 FBIN 30 35 FBIN Y8 VSS 18 31 VSS Y3 19 30 Y8 27 Y9 26 Y3 20 29 Y8 Y9 VDDQ 21 28 VDDQ Y4 22 27 Y9 32 FBOUT 33 Y4 23 26 Y9 FBOUT VSS 24 25 VSS .......................... Document : 38-07464 Rev. *F Page 1 of 8 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY2SSTV857 Pin Description Electrical 1 Pin Number Pin Name I/O Pin Description Characteristics 13, 14 CLK, CLK I Differential Clock Input. LV Differential Input 35 FBIN I Feedback Clock Input. Connect to FBOUT for accessing the Differential Input PLL. 36 FBIN I Feedback Clock Input. Connect to FBOUT for accessing the PLL. 3, 5, 10, 20, 22 Y(0:4) O Clock Outputs Differential Outputs 2, 6, 9, 19, 23 Y (0:4) O Clock Outputs 27, 29, 39, 44, 46 Y(9:5) O Clock Outputs Differential Outputs 26, 30, 40, 43, 47 Y (9:5) O Clock Outputs 32 FBOUT O Feedback Clock Output. Connect to FBIN for normal Differential Outputs operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 33 FBOUT O Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 37 PD I Power Down Input. When PD is set HIGH, all Q and Q outputs are enabled and switch at the same frequency as CLK. When set LOW, all Q and Q outputs are disabled Hi-Z and the PLL is powered down. 4, 11,12,15, 21, 28, VDDQ 2.5V Power Supply for Output Clock Buffers.2.5V Nominal 34, 38, 45 16 AVDD 2.5V Power Supply for PLL. When VDDA is at GND, PLL is 2.5V Nominal bypassed and CLK is buffered directly to the device outputs. During disable (PD = 0), the PLL is powered down. 1, 7, 8, 18, 24, 25, VSS Common Ground 0.0V Ground 31, 41, 42, 48 17 AVSS Analog Ground 0.0V Analog Ground When VDDA is strapped LOW, the PLL is turned off and Zero-delay Buffer bypassed for test purposes. When used as a zero-delay buffer the CY2SSTV857-27 will Power Management likely be in a nested clock tree application. For these applica- tions the CY2SSTV857-27 offers a differential clock input pair Output enable/disable control of the CY2SSTV857-27 allows as a PLL reference. The CY2SSTV857-27 then can lock onto the user to implement power management schemes into the the reference and translate with near-zero delay to low-skew design. Outputs are three-stated/disabled when PD is outputs. For normal operation, the external feedback input, asserted low (see Table 1). FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Note: 1. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (<0.2). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces......................... Document : 38-07464 Rev. *F Page 2 of 8