Si4320 Universal ISM Si4320 Band FSK Receiver PIN ASSIGNMENT DESCRIPTION Silicon Labs Si4320 is a single chip, low power, multi-channel FSK receiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 315, 433, 868, and 915 MHz bands. Used in conjunction with Si4220/21, Silicon Labs FSK transmitters, the Si4320 is a flexible, low cost, and highly integrated solution that does not require production alignments. All required RF Standalone Mode Microcontroller Mode functions are integrated. Only an external crystal and bypass filtering are needed for operation. The Si4320 has a completely integrated PLL for easy RF design, and its This document refers to Si4320-IC Rev J1. rapid settling time allows for fast frequency hopping, bypassing multipath See www.silabs.com/integration for any applicable fading, and interference to achieve robust wireless links. The PLLs high errata. See back page for ordering information. resolution allows the usage of multiple channels in any of the bands. The baseband bandwidth (BW) is programmable to accommodate various FEATURES deviation, data rate, and crystal tolerance requirements. The receiver employs the Zero-IF approach with I/Q demodulation, therefore no external Fully integrated (low BOM, easy design-in) No alignment required in production components (except crystal and decoupling) are needed in a typical Fast settling, programmable, high-resolution PLL application. The Si4320 is a complete analog RF and baseband receiver Fast frequency hopping capability including a multi-band PLL synthesizer with an LNA, I/Q down converter High bit rate (up to 115.2 kbps in digital mode and 256 kbps mixers, baseband filters and amplifiers, and I/Q demodulator. in analog mode) The chip dramatically reduces the load on the microcontroller with Direct differential antenna input integrated digital data processing: data filtering, clock recovery, data Programmable baseband bandwidth (67 to 400 kHz) pattern recognition and integrated FIFO. The automatic frequency control Analog and digital RSSI outputs (AFC) feature allows using a low accuracy (low cost) crystal. To minimize Automatic frequency control (AFC) the system cost, the chip can provide a clock signal for the microcontroller, Data quality detection (DQD) avoiding the need for two crystals. Internal data filtering and clock recovery RX pattern recognition For simple applications, the receiver supports a standalone operation SPI compatible serial control interface mode. This allows complete data receiver operation and control of four Clock and reset signals for microcontroller digital outputs based on the incoming data pattern without a 16 bit RX data FIFO microcontroller. In this mode, 12 or more predefined frequency channels Standalone operation mode without microcontroller can be used in any of the four bands. For low power applications, the Low power duty-cycle mode (less than 0.5 mA average device supports low duty-cycle operation based on the internal wake-up supply current) timer. Standard 10 MHz crystal reference with in circuit calibration Alternative OOK support Wake-up timer FUNCTIONAL BLOCK DIAGRAM Low battery detector 2.2 to 5.4 V supply voltage Low power consumption (~9 mA in low bands) Low standby current (0.3 A) Compact 16-pin TSSOP package TYPICAL APPLICATIONS Remote control Home security and alarm Wireless keyboard/mouse and other PC peripherals Toy control Remote keyless entry Tire pressure monitoring Telemetry Personal/patient data logging Remote automatic meter reading 1 Si4320-DS Rev 1.5r 0308 www.silabs.com Si4320 Data Filtering and Clock Recovery DETAILED DESCRIPTION The output data filtering can be completed by an external capacitor or by using digital filtering according to the final General application. The Si4320 FSK receiver is the counterpart of the Si4220 FSK Analog operation: The filter is an RC type low-pass filter and a transmitter. It covers the unlicensed frequency bands at 315, Schmitt-trigger (St). The resistor (10k) and the St is integrated on 433, 868, and 915 MHz. The device facilitates compliance with the chip. An (external) capacitor can be chosen according to the FCC and ETSI requirements. actual bit-rate. In this mode the receiver can handle up to 256 The receiver employs the Zero-IF approach with I/Q kbps data rate. demodulation, allowing the use of a minimal number of external Digital operation: The data filter is a digital realization of an components in a typical application. The Si4320 consists of a analog RC filter followed by a comparator with hysteresis. In this fully integrated multi-band PLL synthesizer, an LNA with mode there is a clock recovery circuit (CR), which can provide switchable gain, I/Q down converter mixers, baseband filters and synchronized clock to the data. With this clock the received data amplifiers, and an I/Q demodulator followed by a data filter. can fill the RX Data FIFO. The CR has three operation modes: fast, slow, and automatic. In slow mode, its noise immunity is PLL very high, but it has slower settling time and requires more The programmable PLL synthesizer determines the operating accurate data timing than in fast mode. In automatic mode the frequency, while preserving accuracy based on the on-chip CR automatically changes between fast and slow modes. The CR crystal-controlled reference oscillator. The PLLs high resolution starts in fast mode, then automatically switches to slow mode allows for the use of multiple channels in any of the bands. after locking. The RF VCO in the PLL performs automatic calibration, which (Only the data filter and the clock recovery use the bit-rate clock. requires only a few microseconds. Calibration always occurs Therefore, in analog mode, there is no need for setting the when the synthesizer begins. If temperature or supply voltage correct bit-rate.) changes significantly or operational band has changed, VCO recalibration is recommended. Recalibration can be initiated at Data Validity Blocks any time by switching the synthesizer off and back on again. RSSI LNA A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength exceeds a given The LNA has 250 Ohm input impedance, which works well with preprogrammed level. An analog RSSI signal is also available. the recommended antennas. (See Application Notes available from www.silabs.com/integration.) The RSSI settling time depends on the filter capacitor used. Voltage on ARRSI pin vs. Input RF power If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to provide the correct matching and to minimize the noise figure of the receiver. The LNA gain (and linearity) can be selected (0, 6, 14, 20 dB relative to the highest gain) according to RF signal strength. This is useful in an environment with strong interferers. Baseband Filters The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. This allows setting up the receiver according to the characteristics of the signal to be received. An appropriate bandwidth can be selected to accommodate various FSK deviation, data rate, and crystal tolerance P1 -65 dBm 1300 mV requirements. The filter structure is a 7-th order Butterworth low- pass with 40 dB suppression at 2*BW frequency. Offset P2 -65 dBm 1000 mV cancellation is accomplished by using a high-pass filter with a P3 -100 dBm 600 mV cut-off frequency below 7 kHz. See Measurement Results section P4 -100 dBm 300 mV for measured receiver selectivity curves. 2