Si52147-EVB Si52147 EVALUATION BOARD USERS GUIDE Description EVB Features The Si52147 is a nine port PCIe clock generator This document is intended to be used in conjunction compliant to the PCIe Gen1, Gen2 and Gen3 standards. with the Si52147 device and data sheet for the following The Si52147 is a 48-pin QFN device that operates on a tests: 3.3 V power supply and can be controlled using SMBus PCIe Gen1, Gen2, Gen3 compliancy signals along with hardware control input pins.The Power consumption test differential outputs support spread spectrum and can be Jitter performance controlled through SSON input pin. The Si52147 needs 2 a crystal or clock input of 25 MHz. The connections are Testing out I C code for signal tuning described in this document. In-system validation where SMA connectors are present External DIFF8 connection DIFF7 connection Power connectors Clock Input for application for application VDD = 3.3 V power supply GND CKPWRGD/Power down enable DIFF6 SDATA/SCLK SDATA SCLK connection GND for application DIFF0 Output Enable DIFF5 Si52147 DIFF1 Output Enable connection Spread Enable Control for application DIFF2 Output Enable DIFF3 Output Enable DIFF4/DIFF5 Output Enable DIFF6/DIFF8 Output Enable DIFF4 connection for application DIFF0 connection for application DIFF2 connection DIFF3 connection DIFF1 connection for for application application for application Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 10, 2021 1. Front Panel Figure 1. Evaluation Module Front Panel Table 1. Input Jumper Settings Jumper Label Type Description OE0 I OE0, 3.3 V Input for Enabling DIFF0 Clock Output. 1 = DIFF0 enabled, 0 = DIFF0 disabled. OE1 I OE1, 3.3 V Input for Enabling DIFF1 Clock Output. 1 = DIFF1 enabled, 0 = DIFF1 disabled. OE2 I OE2, 3.3 V Input for Enabling DIFF2 Clock Output. 1 = DIFF2 enabled, 0 = DIFF2 disabled. OE3 I OE3, 3.3 V Input for Enabling DIFF3 Clock Output. 1 = DIFF3 enabled, 0 = DIFF3 disabled. OE4/5 I OE4/5, 3.3 V Input for Enabling DIFF4 and DIFF5 Clock Outputs. 1 = DIFF4 & DIFF5 enabled, 0 = DIFF4 & DIFF5 disabled. OE6/8 I OE6/8, 3.3 V Input for Enabling DIFF6, DIFF7 and DIFF8 Clock Outputs. 1 = DIFF6, DIFF7 & DIFF8 enabled, 0 = DIFF6, DIFF7 & DIFF8 disabled. CLKPWGD/PD I 3.3 V LVTTL Input. After CLKPWGD (active high) assertion, this pin becomes a real-time input for asserting power down (active low). 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 10, 2021