Si5316 PRECISION CLOCK JITTER ATTENUATOR Features Fixed frequency jitter attenuator Dual clock inputs with integrated with selectable clock ranges at clock select mux 19, 38, 77, 155, 311, and One clock input can be 1x, 4x, or 622 MHz (710 MHz max) 32x the frequency of the second Support for SONET, 10GbE, clock input 10GFC, and corresponding FEC Single clock output with rates selectable signal format: Ultra-low jitter clock output with LVPECL, LVDS, CML, CMOS jitter generation as low as LOL, LOS alarm outputs 0.3 ps (50 kHz80 MHz) RMS Pin programmable settings Ordering Information: Integrated loop filter with On-chip voltage regulator for 1.8 See page 20. selectable loop bandwidth 5%, 2.5 10%, or 3.3 V 10% (100 Hz7.9 kHz) operation Meets OC-192 GR-253-CORE Small size (6 x 6 mm 36-lead Pin Assignments jitter specifications QFN) Si5316 Pb-free, RoHS compliant Applications Optical modules ITU G.709 line cards SONET/SDH OC-48/OC-192/ Wireless basestations STM-16/STM-64 line cards Test and measurement 10GbE, 10GFC line cards Synchronous Ethernet Description The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC-192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter- attenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 15% higher than nominal Patents pending SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range. The Si5316 is based on Silicon Laboratories 3rd-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5316 is ideal for providing jitter attenuation in high performance timing applications. Rev. 1.0 7/12 Copyright 2012 by Silicon Laboratories Si5316 Si5316 Functional Block Diagram 2 Rev. 1.0