Product Information

SI5348A-D-GM

SI5348A-D-GM electronic component of Silicon Labs

Datasheet
Clock Synthesizer Jitter Cleaner Network synchronizer and jitter attenuator

Manufacturer: Silicon Labs
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 42.895 ea
Line Total: USD 42.9

529 - Global Stock
Ships to you between
Thu. 09 May to Mon. 13 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
529 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1

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SI5348A-D-GM
Silicon Labs

1 : USD 42.895
10 : USD 42.1935
260 : USD 42.182

     
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Si5348 Rev E Data Sheet Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary KEY FEATURES (T-BC) and Slave (T-SC) Clocks Three independent DSPLLs in a single The Si5348 combines the industrys smallest footprint and lowest power network syn- monolithic IC supporting flexible SyncE/ chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The IEEE 1588 and SETS architectures Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless Ultra-low jitter of 95 fs communications systems, and data center switches requiring both traditional and packet Enhanced hitless switching minimizes based network synchronization. output phase transients The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE Input frequency range: 1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can External crystal: 48 to 54 MHz also be used in legacy SETS systems needing Stratum 3/3E compliance. The optional REF clock: 5 to 250 MHz digitally controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt Diff clock: 8 kHz to 750 MHz for 1588 (PTP) clock steering applications. The unique design of the Si5348 allows LVCMOS clock: 8 kHz to 250 MHz the TCXO/OCXO reference input to determine the devices frequency accuracy and Output frequency range: stability. The Si5348 is programmable via a serial interface with in-circuit programmable Differential: 1 PPS to 718.5 MHz non-volatile memory so it always powers up into a known configuration. Programming LVCMOS: 1 PPS to 250 MHz the Si5348 is easy with ClockBuilder Pro software. Factory pre-programmed devices Meets the requirements of: are also available. ITU-T G.8262 (SyncE) EEC Options 1 and 2 Applications: ITU-T G.812 Type III, IV Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2 ITU-T G.813 Option 1 Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2 Telcordia GR-1244, GR-253 IEEE 1588 (PTP) slave clock synchronization (Stratum-3/3E) Stratum 3/3E, G.812, G.813 network synchronization 48-54 MHz XTAL XA XB OSC REF TCXO/ OCXO REFb IN3 INT OUT0 IN4 DSPLL D INT OUT1 INT OUT2 IN0 FRAC IN1 FRAC DSPLL C INT OUT3 IN2 INT OUT4 FRAC INT OUT5 DSPLL A INT OUT6 Status Flags Status Monitor I2C / SPI Control NVM Si5348 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 1 Rev. 0.95 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 3, 2021 1Si5348 Rev E Data Sheet Feature List 1. Feature List The Si5348 features are listed below: Three independent DSPLLs in a single monolithic IC support- Pin or software controllable DCO on each DSPLL with typical ing flexible SyncE/IEEE 1588 and SETS architectures resolution to 1 ppt/step Ultra-Low Jitter TCXO/OCXO reference input determines DSPLL free-run/hold- 95 fs typ (12 kHz to 20 MHz) over accuracy and stability Meets the requirements of: Programmable jitter attenuation bandwidth per DSPLL: 0.001 Hz to 4 kHz ITU-T G.8273.2 T-BC Highly configurable output drivers: LVDS, LVPECL, LVCMOS, ITU-T G.8262 (SyncE) EEC Options 1 & 2 HCSL, CML ITU-T G.812 Type III, IV Core voltage: ITU-T G.813 Option 1 VDD: 1.8 V 5% Telcordia GR-1244, GR-253 (Stratum-3/3E) VDDA: 3.3 V 5% Each DSPLL generates any output frequency from any input Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V frequency Built-in power supply filtering Input frequency range: Status monitoring: LOS, OOF, LOL External crystal: 4854 MHz 2 Serial Interface: I C or SPI (3-wire or 4-wire) REF clock: 5250 MHz ClockBuilder Pro software simplifies device configuration Diff clock: 8 kHz750 MHz 5 input, 7 output, 64 QFN LVCMOS clock: 8 kHz250 MHz Temperature range: 40 to +85 C Output frequency range: Pb-free, RoHS-6 compliant Differential: 1 PPS to 718.5 MHz LVCMOS: 1 PPS to 250 MHz Independent Frequency-on-the-fly for each DSPLL Enhanced hitless switching minimizes output phase transi- ents for 8 kHz, 19.44 MHz, 25 MHz, and all other input fre- quencies. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 Rev. 0.95 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 3, 2021 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

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