SL2305SC-1 Silicon Labs

SL2305 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features Description The SL2305 is a low skew, low jitter and low power Zero 10 to 140 MHz operating frequency range Delay Buffer (ZDB) designed to produce up to five (5) clock Low output clock jitter: outputs from one (1) reference input clock for high speed - 140 ps-max c-c-j at 66 MHz clock distribution applications. The product has an on-chip Low output-to-output skew: 150 ps-max PLL which locks to the input clock at CLKIN and receives its Low product-to-product skew: 400 ps-max feedback internally from the CLKOUT pin. 3.3 V power supply range The SL2305 is available with two (2) drive strength versions. Low power dissipation: The -1 is the standard-drive version and -1H is the high- drive version. - 14 mA-max at 66MHz - 26 mA-max at 133 MHz The SL2305 high-drive version operates up to 140MHz and One input drives 5 outputs organized as 4+1 the standard drive version -1 operates up to 100. SpreadThru PLL that allows use of SSCG The SL2305 enter into Power-Down (PD) mode if the input Standard and High-Drive options at CLKIN is DC (0 to VDD). In this power-down state all five (5) outputs are tri-stated and the PLL is turned off leading to Available in 8-pin SOIC and TSSOP packages less than 12A-max of power supply current draw. Available in Commercial and Industrial grades Benefits Applications Up to five (5) distribution of input clock Printers and MFPs Standard and High-Drive levels to control impedance Digital Copiers level, frequency range and EMI PCs and Work Stations Low jitter and skew DTV Low power dissipation Routers, Switchers and Servers Low cost Digital Embeded Systems Block Diagram PLL CLKOUT CLKIN CLK1 CLK2 CLK3 CLK4 VDD GND Rev 0.1 9/13 Page 1 of 11 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL2305 Pin Configuration CLKIN 1 8 CLKOUT 2 CLK4 CLK2 7 3 6 CLK1 VDD 4 5 GND CLK3 8-Pin SOIC or TSSOP Pin Description Pin Pin Name Pin Type Pin Description Number 1 CLKIN Input Reference Frequency Clock Input. Weak pull-down (250k). 2 CLK2 Output Buffered Clock Output Weak pull-down (250k). 3 CLK1 Output Buffered Clock Output. Weak pull-down (250k). 4 GND Power Power Ground. 5 CLK3 Output Buffered Clock Output. Weak pull-down (250k). 6 VDD Power 3.3V Power Supply. 7 CLK4 Output Buffered Clock Output. Weak pull-down (250k). 8 CLKOUT Output Buffered Clock Output, Used for Internal Feedback to PLL Input. Weak pull- down (250k). Rev 0.1 9/13 Page 2 of 11