S34MS02G104BHI010

S34MS01G1 S34MS02G1 S34MS04G1 1-bit ECC, x8 and x16 I/O, 1.8V V CC SLC NAND Flash for Embedded Distinctive Characteristics Density NAND Flash Interface 1 Gbit / 2 Gbit / 4 Gbit Open NAND Flash Interface (ONFI) 1.0 compliant Address, Data and Commands multiplexed Architecture Input / Output Bus Width: 8-bits / 16-bits Supply Voltage Page Size: 1.8V device: Vcc = 1.7V ~ 1.95V x8 = 2112 (2048 + 64) bytes 64 bytes is spare area Security x16 = 1056 (1024 + 32) words 32 words is spare area One Time Programmable (OTP) area Block Size: 64 Pages Hardware program/erase disabled during power transition x8 = 128k + 4k bytes Additional Features x16 = 64k + 2k words 2 Gb and 4 Gb parts support Multiplane Program and Erase Plane Size: commands 1 Gbit / 2 Gbit: 1024 Blocks per Plane Supports Copy Back Program x8 = 128M + 4M bytes 2 Gb and 4 Gb parts support Multiplane Copy Back Program x16 = 64M + 2M words Supports Read Cache 4 Gbit: 2048 Blocks per Plane Electronic Signature x8 = 256M + 8M bytes Manufacturer ID: 01h x16 = 128M + 4M words Device Size: Operating Temperature 1 Gbit: 1 Plane per Device or 128 Mbyte Industrial: -40C to 85C 2 Gbit: 2 Planes per Device or 256 Mbyte Industrial Plus: -40C to 105C 4 Gbit: 2 Planes per Device or 512 Mbyte Performance Page Read / Program Reliability Random access: 25 s (Max) 100,000 Program / Erase cycles (Typ) (with 1 bit ECC per 528 bytes (x8) or 264 words (x16)) Sequential access: 45 ns (Min) 10 Year Data retention (Typ) Program time / Multiplane Program time: 250 s (Typ) Blocks zero and one are valid and will be valid for at least 1000 Block Erase (S34MS01G1) program-erase cycles with ECC Block Erase time: 2.0 ms (Typ) Package Options Block Erase / Multiplane Erase (S34MS02G1, S34MS04G1) Lead Free and Low Halogen Block Erase time: 3.5 ms (Typ) 48-Pin TSOP 12 x 20 x 1.2 mm 63-Ball BGA 9 x 11 x 1 mm Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00330 Rev. *I Revised May 09, 2016S34MS01G1 S34MS02G1 S34MS04G1 Contents Distinctive Characteristics .................................................. 1 5.7 Program / Erase Characteristics................................... 36 Performance.......................................................................... 1 6. Timing Diagrams......................................................... 37 6.1 Command Latch Cycle.................................................. 37 1. General Description..................................................... 3 6.2 Address Latch Cycle..................................................... 38 1.1 Logic Diagram................................................................ 4 6.3 Data Input Cycle Timing................................................ 38 1.2 Connection Diagram ...................................................... 5 6.4 Data Output Cycle Timing (CLE=L, WE =H, ALE=L, 1.3 Pin Description............................................................... 6 WP =H) ........................................................................ 39 1.4 Block Diagram................................................................ 7 6.5 Data Output Cycle Timing (EDO Type, CLE=L, WE =H, 1.5 Array Organization......................................................... 8 ALE=L).......................................................................... 39 1.6 Addressing..................................................................... 9 6.6 Page Read Operation ................................................... 40 1.7 Mode Selection ............................................................ 12 6.7 Page Read Operation (Interrupted by CE ).................. 41 2. Bus Operation ............................................................ 13 6.8 Page Read Operation Timing with CE Dont Care...... 42 2.1 Command Input ........................................................... 13 6.9 Page Program Operation.............................................. 42 2.2 Address Input............................................................... 13 6.10 Page Program Operation Timing with CE Dont Care. 43 2.3 Data Input .................................................................... 13 6.11 Page Program Operation with Random Data Input ...... 43 2.4 Data Output.................................................................. 13 6.12 Random Data Output In a Page ................................... 44 2.5 Write Protect ................................................................ 13 6.13 Multiplane Page Program Operation S34MS02G1 and 2.6 Standby........................................................................ 13 S34MS04G1 ................................................................. 44 6.14 Block Erase Operation.................................................. 45 3. Command Set............................................................. 14 6.15 Multiplane Block Erase S34MS02G1 and S34MS04G1 3.1 Page Read................................................................... 15 46 3.2 Page Program.............................................................. 15 6.16 Copy Back Read with Optional Data Readout.............. 47 3.3 Multiplane Program S34MS02G1 and S34MS04G1 16 6.17 Copy Back Program Operation With Random Data Input.. 3.4 Page Reprogram S34MS02G1 and S34MS04G1... 16 47 3.5 Block Erase.................................................................. 17 6.18 Multiplane Copy Back Program S34MS02G1 and 3.6 Multiplane Block Erase S34MS02G1 and S34MS04G1 S34MS04G1 ................................................................. 48 18 6.19 Read Status Register Timing........................................ 49 3.7 Copy Back Program..................................................... 18 6.20 Read Status Enhanced Timing ..................................... 50 3.8 EDC Operation S34MS02G1 and S34MS04G1...... 19 6.21 Reset Operation Timing................................................ 50 3.9 Read Status Register................................................... 21 6.22 Read Cache.................................................................. 51 3.10 Read Status Enhanced S34MS02G1 and S34MS04G1 6.23 Cache Program............................................................. 53 21 6.24 Multiplane Cache Program S34MS02G1 and 3.11 Read Status Register Field Definition.......................... 22 S34MS04G1 ................................................................. 54 3.12 Reset............................................................................ 22 6.25 Read ID Operation Timing ............................................ 56 3.13 Read Cache................................................................. 22 6.26 Read ID2 Operation Timing .......................................... 56 3.14 Cache Program............................................................ 23 6.27 Read ONFI Signature Timing........................................ 57 3.15 Multiplane Cache Program S34MS02G1 and 6.28 Read Parameter Page Timing ...................................... 57 S34MS04G1 ................................................................ 24 6.29 OTP Entry Timing ......................................................... 58 3.16 Read ID........................................................................ 25 6.30 Power On and Data Protection Timing ......................... 58 3.17 Read ID2...................................................................... 27 6.31 WP Handling............................................................... 59 3.18 Read ONFI Signature .................................................. 27 7. Physical Interface ....................................................... 60 3.19 Read Parameter Page ................................................. 28 3.20 One-Time Programmable (OTP) Entry ........................ 30 7.1 Physical Diagram.......................................................... 60 4. Signal Descriptions ................................................... 30 8. System Interface ......................................................... 62 4.1 Data Protection and Power On / Off Sequence ........... 30 9. Error Management ...................................................... 64 4.2 Ready/Busy.................................................................. 31 9.1 System Bad Block Replacement................................... 64 4.3 Write Protect Operation ............................................... 32 9.2 Bad Block Management................................................ 65 5. Electrical Characteristics.......................................... 33 10. Ordering Information.................................................. 66 5.1 Valid Blocks ................................................................. 33 11. Revision History.......................................................... 67 5.2 Absolute Maximum Ratings ......................................... 33 5.3 AC Test Conditions...................................................... 33 5.4 AC Characteristics ....................................................... 34 5.5 DC Characteristics....................................................... 35 5.6 Pin Capacitance........................................................... 35 Document Number: 002-00330 Rev. *I Page 2 of 75