74AC257TTR

74AC257 QUAD 2 CHANNEL MULTIPLEXER (3-STATE) HIGH SPEED: t = 4.5ns (TYP.) at V = 5V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC 50 TRANSMISSION LINE DRIVING DIP SOP TSSOP CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: I = I = 24mA (MIN) OH OL BALANCED PROPAGATION DELAYS: ORDER CODES t t PLH PHL PACKAGE TUBE T & R OPERATING VOLTAGE RANGE: DIP 74AC257B V (OPR) = 2V to 6V CC SOP 74AC257M 74AC257MTR PIN AND FUNCTION COMPATIBLE WITH TSSOP 74AC257TTR 74 SERIES 257 IMPROVED LATCH-UP IMMUNITY high impedance state. If SELECT input is held DESCRIPTION LOW, data is selected, when SELECT input is held HIGH, data is chosen. The 74AC257 is an advanced high-speed CMOS All inputs and outputs are equipped with QUAD 2-CHANNEL MULTIPLEXER (3-STATE) protection circuits against static discharge, giving fabricated with sub-micron silicon gate and 2 them 2KV ESD immunity and transient excess double-layer metal wiring C MOS tecnology. voltage. It is composed of four independent 2-channel multiplexer with common SELECT and ENABLE (OE) inputs. It is a non-inverting multiplexer. When the OE input is held HIGH,all the output become in PIN CONNECTION AND IEC LOGIC SYMBOLS April 2001 1/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) 74AC257 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 SELECT Common Data Select Inputs 2, 5, 11, 14 1A to 4A Data Inputs From Source A 3, 6, 10, 13 1B to 4B Data Inputs From Source B 4, 7, 9, 12 1Y to 4Y Multiplexer Outputs 15 OE 3 State Output Enable Inputs (Active LOW) 8 GND Ground (0V) 16 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUT OE SELECT A B Y HX XX L LLL X L LL H X H LH X L L LH X H H X : Dont Care Z : High Impedance LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)