74ACT374 OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS (NON INVERTED) HIGH SPEED: f = 260MHz (TYP.) at V = 5V MAX CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A COMPATIBLE WITH TTL OUTPUTS V = 2V (MIN.), V = 0.8V (MAX.) IH IL DIP SOP TSSOP 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: I = I = 24mA (MIN) OH OL ORDER CODES BALANCED PROPAGATION DELAYS: PACKAGE TUBE T & R t t PLH PHL DIP 74ACT374B OPERATING VOLTAGE RANGE: SOP 74ACT374M 74ACT374MTR V (OPR) = 4.5V to 5.5V CC TSSOP 74ACT374TTR PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 IMPROVED LATCH-UP IMMUNITY a normal logic state (high or low logic level) when the OE is high the outputs go to the high DESCRIPTION impedance state. The output control does not affect the internal The 74ACT374 is an advanced high-speed CMOS operation of flip-flops that is, the old data can be OCTAL D-TYPE FLIP-FLOP with 3 STATE retained or the new data can be entered even OUTPUT NON INVERTING fabricated with while the outputs are off. sub-micron silicon gate and double-layer metal 2 This device is designed to interface directly High wiring C MOS technology. Speed CMOS systems with TTL and NMOS These 8 bit D-Type Flip-Flop are controlled by a components. clock input (CK) and an output enable input (OE). All inputs and outputs are equipped with On the positive transition of the clock, the Q protection circuits against static discharge, giving outputs will be set to the logic that were setup at them 2KV ESD immunity and transient excess the D inputs. voltage. While the (OE) input is low, the 8 outputs will be in PIN CONNECTION AND IEC LOGIC SYMBOLS April 2001 1/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) 74ACT374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1OE 3-State Output Enable (Active LOW) 2, 5, 6, 9, 12, Q0 to Q7 3-State Outputs 15, 16,19 3, 4, 7, 8, 13, D0 to D7 Data Inputs 14, 17, 18 11 CK Clock Input (LOW-to-HIGH Edge Trigger) 10 GND Ground (0V) 20 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUT OE CK D Q H XXZ L X NO CHANGE LLL H LH X : Dont Care Z : High Impedance LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)