E-ST10F269-DP

ST10F296E 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM Features High performance 16-bit CPU with DSP functions 31.25 ns instruction cycle time at 64 MHz max CPU clock Multiply/accumulate unit (MAC) 16 x 16-bit PBGA 208 multiplication, 40-bit accumulator (23 x 23 x 1.96 mm) Enhanced boolean bit manipulation facilities Serial channels Single-cycle context switching support Two synchronous/asynch. serial channels Memory organization Two high-speed synchronous channels 512 Kbyte Flash memory (32-bit fetch) 2 I C standard interface 320 Kbyte extension Flash memory Two CAN 2.0B interfaces operating on one or (16-bit fetch) two CAN busses (64 or 2 x 32 message 100 k erasing/programming cycles objects, C-CAN version) Up to 16 Mbyte linear address space for Fail-safe protection 2 code and data (5 Mbytes with CAN or I C) Programmable watchdog timer 2 Kbyte on-chip internal RAM (IRAM) Oscillator watchdog 66 Kbyte on-chip extension RAM (XRAM) On-chip bootstrap loader Programmable external bus characteristics for different address ranges Clock generation Five programmable chip-select signals On-chip PLL and 4-12 MHz oscillator Hold-acknowledge bus arbitration support Direct or prescaled clock input Interrupt Real-time clock 8-channel peripheral event controller for Up to 143 general purpose I/O lines single cycle interrupt driven data transfer Individually programmable as input, output 16-priority-level interrupt system with 56 or special function sources, sampling rate down to 15.6 ns Programmable threshold (hysteresis) Timers Idle, power-down and stand-by modes Two multi-functional general purpose timer single voltage supply: 5 V 10% (embedded units with 5 timers regulator for 1.8 V core supply). Two 16-channel capture/compare units Table 1. Device summary Analog-to-digital converter (ADC) 32-channel 10-bit Temp. range CPU freq. range Order codes (C) (MHz) 3 s minimum conversion time TImer for ADC channel injection ST10F296 -40 to 125 1 to 64 4-channel PWM unit and 4-channel XPWM ST10F296TR October 2008 Rev 2 1/346 www.st.com 1 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Contents ST10F296E Contents 1 Description 17 2 Ball data 20 3 Functional description 32 4 Memory organization . 33 4.1 IFlash 33 4.2 XFlash . 34 4.3 Internal RAM (IRAM) 34 4.4 Extension RAM (XRAM) 35 4.5 Special function register (SFR) areas . 35 4.6 CAN1 35 4.7 CAN2 36 4.8 Real-time clock (RTC) . 36 4.9 Pulse-width modulation 1 (PWM1) 36 4.10 ASC1 36 4.11 SSC1 36 2 4.12 I C 37 4.13 XTimer/XMiscellaneous 37 4.14 XPort 9/XPort 10 . 37 4.15 Visibility of XBus peripherals 37 4.16 XPeripheral configuration registers . 39 5 Internal Flash memory 42 5.1 Functional description . 42 5.1.1 Structure 42 5.1.2 Module structure 43 5.1.3 Low power mode 45 5.2 Write operation . 45 5.2.1 Power supply drop . 46 5.3 Internal Flash memory registers 46 2/346 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)