EVL4984-350W 350 W CCM PFC pre-regulator demonstration board based on the L4984D Data brief Description The EVL4984-350W demonstration board, based on the new L4984D continuous conduction mode PFC controller, implements a 350 W wide-range input PFC pre-conditioner. It is suitable for all SMPS from 150 W to several kWs, and is compliant with IEC61000-3-2 and JEITA-MITI standards. Features Line voltage range: 90 to 265 V ac Minimum line frequency (fL): 47 Hz Regulated output voltage: 400 V Rated output power: 350 W Maximum 2 fL output voltage ripple: 12.5 V (peak-to-peak) Hold-up time: 20 ms (VDROP after hold-up time: 300 V) Switching frequency: 70 kHz Minimum efficiency: 94% (at V = 90 V , in ac P = 350 W) out PCB: single-side, 70 um, CEM-1, 112 x 114 mm May 2013 DocID023720 Rev 2 1/10 For further information contact your local STMicroelectronics sales office. www.st.com 10General information and electrical schematics EVL4984-350W 1 General information and electrical schematics The main purpose of a PFC pre-conditioner is to correct input current distortion in order to decrease the harmonic contents below the limits of the relevant regulations. Therefore, this demonstration board has been tested in accordance with the European standard EN61000- 3-2 Class-D and Japanese standard JEITA-MITI Class-D at full load and at both the nominal input voltage mains. The power stage of the PFC is a traditional boost PFC converter, connected to the output of the rectifier bridge D2. It is made up of the boost inductor L3, the power switch consisting of the parallel of MOSFETs Q1 and Q2, diode D3, and the output capacitors C3 and C4. The 300 V varistor RV1, connected between the line and neutral, protects the circuit against high input voltage transients, while the F1 fuse disconnects the mains in case of short- circuit. To meet EMC standards, the board is equipped with an input EMI filter, cutting the switching noise coming from the boost stage. In particular, L2 filters common mode emissions while L1, C1, and C2 reduce differential mode emissions. The L4984D must be supplied by an external power supply, connected between pin 1 (VCC) and pin 2 (GND) of J3. The capacitor C14, connected to the TIMER ( 7) pin, determines the switching frequency. The resistor divider R12, R16, R22 and R24 provides the information regarding the instantaneous mains voltage to the L4984D multiplier (MULT, 3), which is used to modulate the peak current of the boost and the TOFF duration, and is fed to the VFF block. The resistors R6, R8, R13 with R17 and R18 are dedicated to sensing the output voltage and feeding, to the inverting input of the error amplifier (INV, 1), the feedback information necessary to keep the output voltage regulated. Between the INV ( 1) and COMP ( 2) pins, components C8, R21 and C11 form the error amplifier compensation network to maintain the required loop stability. The inductor peak current is sensed by resistors R27, R30, and R31 placed in series with the MOSFET source and the derived signal is fed into the current sense pin (CS, 4) of the L4984D via the filter by R29 and C13. C15 and R28, connected to the VFF pin ( 5), complete an internal peak-holding circuit providing information on the RMS mains voltage, deriving a DC voltage equal to the peak of the MULT ( 3) voltage, which is fed to the multiplier to compensate the control loop gain dependence on the mains voltage. The brownout function is also implemented by this pin. A voltage below 0.8 V on the VFF pin ( 5) shuts down (no latch) the IC and brings its consumption to a considerably lower level. The L4984D starts as the voltage at the pin rises above 0.88 V. The divider R5, R10, R14 and R23 provides the information regarding the output voltage level to the L4984D PFC OK pin ( 7), to implement the so-called dynamic OVP protection, preventing the output voltage from excessive values during the load transients due to the slow response caused by the intrinsic narrow bandwidth of PFC systems. If the voltage on the PFC OK pin ( 7) exceeds 2.5 V, the L4984D stops switching, and restarts as the voltage on the pin falls below 2.4 V. The open loop protection (also called feedback failure protection) is realized by monitoring the PFC OK ( 7) and INV ( 1) pins. If the voltage on the PFC OK pin ( 7) exceeds 2.5 V, and at the same time the voltage on the INV pin ( 1) falls below 1.66 V, a feedback failure is assumed and the device is latched off. Normal operation can be resumed only by cycling 2/10 DocID023720 Rev 2