L4972AD STMicroelectronics

L4972A 2A SWITCHING REGULATOR 1 Features Figure 1. Packages 2A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REG. PowerDIP20 (16+2+2) SO20 INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE Table 1. Order Codes RESET AND POWER FAIL FUNCTIONS Part Number Package INPUT/OUTPUT SYNC PIN L4972A DIP20 (16+2+20) UNDER VOLTAGE LOCK OUT WITH L4972AD SO20 HYSTERETIC TURN-ON L4972AD013TR SO20 in Tape & Reel PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY uses a DMOS output transistor to obtain very high SWITCHING FREQUENCY UP TO 200KHz efficiency and very fast switching times. Features THERMAL SHUTDOWN of the L4972 include reset and power fail for micro- CONTINUOUS MODE OPERATION processors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mounted in a Powerdip 16 + 2 + 2 and SO20 2 Description large plastic packages and requires few external The L4972A is a stepdown monolithic power components. Efficient operation at switching fre- switching regulator delivering 2A at a voltage vari- quencies up to 200KHz allows reduction in the able from 5.1 to 40V. size and cost of external filter component. Realized with BCD mixed technology, the device Figure 2. Block Diagram Rev. 3 May 2005 1/22L4972A Table 2. Pin Description N Pin Function 1 BOOTSTRAP A C capacitor connected between this terminal and the output allows to drive boot properly the internal D-MOS transistor. 2 RESET DELAY A C capacitor connected between this terminal and ground determines the reset d signal delay time. 3 RESET OUT Open Collector Reset/power Failand the output voltages are safe. Signal Output. This output is high when the supply 4 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. 5, 6 15, GROUND Common Ground Terminal 16 7 FREQUENCY A series RC network connected between this terminal and ground determines the COMPENSATION regulation loop gain characteristics. 8 SOFT START Soft Start Time Constant. A capacitor is connected between the sterminal and ground to define the soft start time constant. 9 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation It is connected via a divider for higher voltages. 10 SYNC INPUT Multiple L4972As are synchronized by connecting pin 10 inputs together or via an external syncr. pulse. 11 SUPPLY VOLTAGE Unregulated Input Voltage. 12, 19 N.C. Not Connected. 13 V 5.1V V Device Reference Voltage. ref ref 14 V Internal Start-up Circuit to Drive the Power Stage. start 17 OSCILLATOR R . External resistor connected to ground determines the constant charging osc current of C . osc 18 OSCILLATOR C . External capacitor connected to ground determines (with R ) the switching osc osc frequency. 20 OUTPUT Regulator Output. Figure 3. Pin Connection (Top view) BOOTSTRAP 1 20 OUTPUT RESET DELAY 2 19 N.C. RESET OUT 3 18 C OSC P. FAIL INPUT 4 17 R OSC GND 5 16 GND GND 6 15 GND FREQ. COMP. 7 14 Vstart SOFT START 8 13 Vref FEEDBACK IN. 9 12 N.C. SYNC INPUT 10 11 Vi DIP20 2/22