L6751B Digitally controlled dual PWM for Intel VR12 and AMD SVI Datasheet production data Features VR12 compliant with 25 MHz SVID bus rev1.5 SerialVID with programmable IMAX, TMAX, VBOOT, ADDRESS AMD SVI compliant Second generation LTB Technology QFN68 8x8 mm Flexible driver/DrMOS support JMode support Description Fully configurable through PMBus The L6751B is a universal digitally controlled dual Dual controller: PWM DC-DC designed to power Intels VR12 and up to 6 phases for CORE and memory AMD SVI processors and memories: all required 1 phase for graphics (GFX), system agent parameters are programmable through dedicated (VSA) or Northbridge (VDDNB) pinstrapping and PMBus interface. Single NTC design for TM, LL and Imon The device features up to 6-phase programmable thermal compensation (for each section) operation for the multi-phase section and a single- VFDE and GDC - gate drive control for phase with independent control loops. When efficiency optimization configured for memory supply, single-phase (VTT) reference is always tracking multi-phases DPM - dynamic phase management (VDDQ) scaled by a factor of 2. The L6751B Dual remote sense 0.5% Vout accuracy supports power state transitions featuring VFDE, Full-differential current sense across DCR programmable DPM and GDC maintaining the best efficiency over all loading conditions without AVP - adaptive voltage positioning compromising transient response. The device Dual independent adjustable oscillator assures fast and independent protection against Dual current monitor load overcurrent, under/overvoltage and feedback disconnections. Pre-biased output management Average and per-phase OC protection The device is available in VFQFPN68 8x8 mm package. OV, UV and FB disconnection protection Dual VR RDY Table 1. Device summary VFQFPN68 8x8 mm package Order code Package Packaging L6751B Tray Applications VFQFPN68 8x8 mm L6751BTR Tape and reel High-current VRM / VRD for desktop / server / workstation Intel / AMD CPUs DDR3 memory supply December 2012 Doc ID 024028 Rev 1 1/58 This is information on a product in full production. www.st.com 58Contents L6751B Contents 1 Typical application circuit and block diagram 6 1.1 Application circuit 6 1.2 Block diagram . 7 2 Pin description and connection diagram 8 2.1 Pin description 8 2.2 Thermal data 15 3 Electrical specifications . 16 3.1 Absolute maximum ratings 16 3.2 Electrical characteristics 16 4 Device configuration and pinstrapping tables . 20 4.1 JMode . 20 4.2 Programming HiZ level . 21 5 Device description and operation . 28 6 Output voltage positioning . 29 6.1 Multi-phase section - phase programming 29 6.2 Multi-phase section - current reading and current sharing loop 29 6.3 Multi-phase section - defining load-line 30 6.4 Single-phase section - disable . 31 6.5 Single-phase section - current reading . 31 6.6 Single-phase section - defining load-line . 31 6.7 Dynamic VID transition support 32 6.7.1 LSLESS startup and pre-bias output . 33 6.8 DVID optimization: REF/SREF . 33 7 Output voltage monitoring and protection 34 7.1 Overvoltage . 35 7.2 Overcurrent and current monitor . 35 7.2.1 Multi-phase section 35 2/58 Doc ID 024028 Rev 1