LD39100PU33RY

LD39100 Automotive grade 1 A, low quiescent current, low-noise voltage regulator Features AEC-Q100 qualified DFN6 (3x3 mm) Input voltage from 1.5 to 5.5 V Ultra-low dropout voltage (200 mV typ. at 1 A load) Very low quiescent current (20 A typ. at no load, 200 A typ. at 1 A load, 1 A max. in off mode) Very low-noise with no bypass capacitor (30 V at V = 0.8 V) RMS OUT Output voltage tolerance: 2.0% at 25 C 1 A guaranteed output current Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and adjustable from 0.8 Logic-controlled electronic shutdown Stable with ceramic capacitors C = 1 F OUT Internal current and thermal limit DFN6 (3x3 mm) package Temperature range: -40 C to 125 C Applications Printers Game consoles Maturity status link Computer LD39100 Consumer applications Automotive post regulation Description The LD39100 provides 1 A maximum current with an input voltage range from 1.5 V to 5.5 V and a typical dropout voltage of 200 mV. The device is stable with ceramic capacitors on the input and output. The ultra-low dropout voltage, low quiescent current and low-noise features make it suitable for low power battery-powered applications. Power supply rejection is 70 dB at low frequency and starts to roll off at 10 kHz. Enable logic control function puts the LD39100 in shutdown mode, allowing a total current consumption lower than 1 A. The device also includes short-circuit constant current limiting and thermal protection. LD39100 is available also in AEC-Q100 qualified version, in the DFN6 (3x3 mm) with wettable flank package. DS6257 - Rev 9 - April 2020 www.st.com For further information contact your local STMicroelectronics sales office.LD39100 Circuit schematics 1 Circuit schematics Figure 1. LD39100 schematic diagram (adjustable version) IINN PPGG PPoowweerr--ggooodod ssiiggnnaall IIINNN BBaanndGdGaapp rreeffereerennccee CuCurrrreennt t OpOpAmAmpp lliimmiitt OOUUTT TThheerrmmaall pprrootteeccttiioonn ADADJJ EENN InIntteerrnnaall eennaabbllee GGNNDD GIPD010920151332MT Figure 2. LD39100 schematic diagram (fixed version) IINN PPGG PPoowweerr--ggooodod ssiiggnnaall IIINNN BBaanndGdGaapp rreeffereerennccee CCuurrrreennt t OpOpAmAmpp lliimmiitt OOUUTT TThheerrmmaall pprrootteeccttiioonn RR 11 NNCC RR 22 EENN InIntteerrnnaall eennaabbllee GGNNDD GIPD010920151333MT DS6257 - Rev 9 page 2/29