LNBH24LQTR STMicroelectronics

LNBH24L Dual LNBS supply and control IC with step-up and IC interface Features Complete interface between LNBS and IC bus Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% 0.5 A) Selectable output current limit by external resistor Compliant with main satellite receivers output voltage specification QFN32 5 x 5 mm (ePad) Auxiliary modulation input (EXTM) facilitates DiSEqC 1.X encoding Low-drop post regulator and high efficiency step-up PWM with integrated power N-MOS allow low power losses Overload and over-temperature internal protections with IC diagnostic bits Output voltage and output current level diagnostic feedback by IC bits LNB short circuit dynamic protection +/- 4 kV ESD tolerant on output power pins Description Intended for analog and digital DUAL satellite receivers/Sat-TV, Sat-PC cards, the LNBH24L is a monolithic voltage regulator and interface IC, assembled in QFN 5x5 ePAD, specifically designed to provide the 13 / 18 V power supply and the 22 kHz tone signaling for two independent LNB down-converters in the antenna dishes and/or multi-switch box. In this application field, it offers a dual tuner STBs complete solution with extremely low component count, low power dissipation together with simple design and IC standard interfacing. Table 1. Device summary Order code Package Packaging LNBH24LQTR QFN32 5 x 5 (Exposed pad) Tape and reel March 2010 Doc ID 16857 Rev 2 1/25 www.st.com 25Contents LNBH24L Contents 1 Block diagram 4 2 Introduction 5 2.1 Application information (valid for each section A/B) 5 2.2 DiSEqC data encoding 5 2.3 DiSEqC 1.X implementation by EXTM pin . 5 2.4 DISEQC 1.X implementation with VoTX and EXTM pin connection 5 2.5 PDC optional circuit for DISEQC 1.X applications using VoTX signal on to EXTM pin . 6 2.6 IC interface 6 2.7 Output voltage selection . 6 2.8 Diagnostic and protection functions 6 2.9 Over-current and short circuit protection and diagnostic 7 2.10 Thermal protection and diagnostic . 7 2.11 Output current limit selection . 7 3 Pin configuration . 8 4 Maximum ratings . 10 5 Application circuits . 11 6 IC bus interface . 13 6.1 Data validity . 13 6.2 Start and stop condition 13 6.3 Byte format 13 6.4 Acknowledge 13 6.5 Transmission without acknowledge . 13 7 LNBH24 software description 15 7.1 Interface protocol . 15 7.2 System register (SR, 1 Byte for each section A and B) 15 7.3 Transmitted data (IC bus write mode) for each sections A/B . 15 2/25 Doc ID 16857 Rev 2