M74HC280 9-bit parity generator Datasheet - production data Pin and function compatible with 74 series 280 ESD performance HBM: 2 kV MM: 200 V CDM: 1 kV SO14 TSSOP14 Description The M74HC280 is a high-speed CMOS 9-bit parity generator fabricated with silicon gate 2 Features C MOS technology. It is composed of nine data inputs (A to I) and High-speed: odd/even parity outputs ( ODD and EVEN). The t = 22 ns (typ.) at V = 6 V PD CC nine data inputs control the output conditions. Low power dissipation: When the number of high-level inputs is odd, I = 4 A (max.) at T = 25 C CC A ODD outputs are kept high and EVEN outputs High noise immunity: are kept low. Conversely, when the number of V = V = 28 % V (min) NIH NIH CC high-level outputs is even, EVEN outputs are kept high and ODD outputs are kept low. The IC Symmetrical output impedance: generates either odd or even parity making the I = I = 4 mA (min.) OH OL application flexible. The word-length capability is Balanced propagation delays: easily expanded by cascading. t t PLH PHL All inputs are equipped with protection circuits Wide operating voltage range: against static discharge and transient excess V (opr) = 2 V to 6 V CC voltage. Table 1. Device summary Order code Temp. range Package Packing Marking M74HC280RM13TR -55 C to 125 C S014 74HC280 (1) M74HC280YRM13TR -40 C to 125 C SO14 (automotive grade) 74HC280Y Tape and reel M74HC280TTR -55 C to 125 C TSSOP14 HC280 (1) M74HC280YTTR -40 C to 125 C TSSOP14 (automotive grade) HC280Y 1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 and Q002 or equivalent. January 2014 DocID1938 Rev 2 1/14 This is information on a product in full production. www.st.comContents M74HC280 Contents 1 Pin information . 3 2 Functional description . 4 3 Electrical characteristics . 6 4 Package information 10 4.1 SO14 package information .11 4.2 TSSOP14 package information 12 5 Ordering information . 13 6 Revision history . 13 2/14 DocID1938 Rev 2